US5036375A
Expired / Lapsed
US
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Floating-gate memory cell with tailored doping profile
Assignee: Texas Instruments Inc
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Filing: 1990-10-22
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Granted: 1991-07-30
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Expires: 2010-10-22
Abstract
Abstract A floating-gate memory cell with an improved doping profile. After the substrate background doping has been set to a desired level (e.g. by a high dose implant and long drive in), two implants of opposite type are used to shape the doping profile of the floating-gate transistor. A boron implant is used to provide significantly increased p-type doping underneath the channel, at depths near the midpoint of the source/drain diffusions. A shallow arsenic implant partially compensates this boron implant at the surface, to set the threshold voltage as desired. The region of substantially increased p-type doping helps to suppress the lateral parasitic bipolar transistor which can otherwise suppress programmation, and also (by providing increased doping at the drain boundary) increases hot electron generation.
Inventors
- 👤 Allan T. Mitchell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:01
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/314
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
262 words
A floating-gate memory device comprising peripheral transistors and memory transistors, said peripheral transistors comprising n-channel devices, said memory transistors formed on a substrate having a p-type upper portion, said memory transistors each comprising: first and second heavily doped n-type source/drain regions separated to define a channel region in said p-type upper portion; a gate oxide overlying said channel region and a floating gate overlying said gate oxide; a control gate overlying and insulated from said floating gate, wherein the largest value of the net p-type dopant concentration anywhere within the volume of said p-type upper portion extending from 0 to 0.5 micron directly below the interface between said gate oxide and said channel region is more than 1.5 times the net p-type dopant concentration in said channel region at the interface between said gate oxide and said channel region, the maximum value of the net p-type dopant concentration within the upper portion of said substrate occurs at a depth which is shallower than the depth of said source/drain diffusions, the background value of the net p-type dopant concentration within the upper portion of said substrate near said memory transistors is greater than the background value of the net p-type dopant concentration within the upper portion of said substrate near said channel peripheral transistors, and the largest value of the net p-type dopant concentration, within the volume of said p-type upper portion extending from 0 to 0.5 micron directly below the gate oxide-channel region interface, is nearly ten times the background level of the p-type net dopant concentration in said p-type upper portion.
Claim 2
Dependent Claim
262 words
A floating-gate memory device comprising peripheral transistors and memory transistors, said peripheral transistors comprising n-channel devices, said memory transistors formed on a substrate having a p-type upper portion, said memory transistors each comprising: first and second heavily doped n-type source/drain regions separated to define a channel region in said p-type upper portion; a gate oxide overlying said channel region and a floating gate overlying said gate oxide; a control gate overlying and insulated from said floating gate, wherein the largest value of the net p-type dopant concentration anywhere within the volume of said p-type upper portion extending from 0 to 0.5 micron directly below the interface between said gate oxide and said channel region is more than 1.5 times the net p-type dopant concentration in said channel region at the interface between said gate oxide and said channel region, the maximum value of the net p-type dopant concentration within the upper portion of said substrate occurs at a depth which is shallower than the depth of said source/drain diffusions, the background value of the net p-type dopant concentration within the upper portion of said substrate near said memory transistors is greater than the background value of the net p-type dopant concentration within the upper portion of said substrate near said channel peripheral transistors, and the largest value of the net p-type dopant concentration, within the volume of said p-type upper portion extending from 0 to 0.5 micron directly below the gate oxide-channel region interface, is nearly ten times the background level of the p-type net dopant concentration in said p-type upper portion.
Claim 3
Dependent Claim
26 words
The device of claim 1 wherein the background of the p-type net dopant concentration is measured at a two micron depth into said p-type upper portion.
Claim 4
Dependent Claim
235 words
A floating-gate memory device comprising peripheral transistors and memory transistors, said peripheral transistors comprising n-channel devices, said memory transistors each formed on a substrate having a p-type upper portion, said memory transistors each comprising: first and second heavily doped n-type source/drain regions separated to define a channel region in said p-type upper portion; a gate oxide overlying said channel region and a floating gate overlying said gate oxide; a control gate overlying and insulated from said floating gate, wherein the largest value of the net p-type dopant concentration anywhere within the volume of said p-type upper portion extending from 0 to 0.5 micron directly below the interface between said gate oxide and said channel region is more than 1.5 times the net p-type dopant concentration in said channel region at the interface between said gate oxide and said channel region and is also nearly ten times the net p-type background dopant concentration in said p-type upper portion; the maximum value of the net p-type dopant concentration within the upper portion of said substrate occurs at a depth which is shallower than the depth of said source/drain diffusions; and the background value of the net p-type dopant concentration within the upper portion of said substrate near said memory transistor is equal to or greater than the background value of the net p-type dopant concentration within the upper portion of said substrate near said n-channel peripheral transistors.
Claim 5
Dependent Claim
235 words
A floating-gate memory device comprising peripheral transistors and memory transistors, said peripheral transistors comprising n-channel devices, said memory transistors each formed on a substrate having a p-type upper portion, said memory transistors each comprising: first and second heavily doped n-type source/drain regions separated to define a channel region in said p-type upper portion; a gate oxide overlying said channel region and a floating gate overlying said gate oxide; a control gate overlying and insulated from said floating gate, wherein the largest value of the net p-type dopant concentration anywhere within the volume of said p-type upper portion extending from 0 to 0.5 micron directly below the interface between said gate oxide and said channel region is more than 1.5 times the net p-type dopant concentration in said channel region at the interface between said gate oxide and said channel region and is also nearly ten times the net p-type background dopant concentration in said p-type upper portion; the maximum value of the net p-type dopant concentration within the upper portion of said substrate occurs at a depth which is shallower than the depth of said source/drain diffusions; and the background value of the net p-type dopant concentration within the upper portion of said substrate near said memory transistor is equal to or greater than the background value of the net p-type dopant concentration within the upper portion of said substrate near said n-channel peripheral transistors.
Claim 6
Dependent Claim
32 words
The device of claim 3 wherein the background value of the net p-type dopant concentration near said memory transistors is measured at a depth of two microns into the substrate upper portion.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-07-29 | 1995-01-28 | 1995-07-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-07-29 | 1999-01-28 | 1999-07-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-07-29 | 2003-01-28 | 2003-07-30 | $7700.00 | Window Closed / Lapsed |