US4017888A
Expired / Lapsed
US
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Non-volatile metal nitride oxide semiconductor device
Assignee: International Business Machines Corp
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Filing: 1975-12-31
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Granted: 1977-04-12
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Expires: 1995-12-31
Abstract
Abstract A metal nitride oxide semiconductor device capable of use within a memory cell, having a more heavily doped region of the same type as the substrate provided directly under the channel of the depletion mode device. Application of a positive write voltage to the gate of the device, with the substrate at 0 volts potential and the source and drain biased to a suitable positive level, results in avalanche operation of the device whereby charge is stored in a nitride oxide interface under the gate, thereby converting the device to enhancement mode operation. The charge can be removed with the source and drain biased to the 0 volt potential of the substrate and a positive erase signal applied to the gate. A four device memory cell is disclosed.
Inventors
- 👤 Kenneth Howard Christie
- 👤 David DeWitt
- 👤 William Stanford Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:46
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0413; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0466; H10D30/60; H10D30/69; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/371; H10D84/00; H10D84/80; H10D84/82; H10D84/83
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
123 words
A memory element comprising a conductive substrate of one conductivity type having first and second spaced apart regions of another conductivity forming a source and a drain for the element, respectively, said regions being interconnected by a thin region of said other conductivity type forming a channel between the source and drain; first and second insulating layers on the surface of said substrate overlying said channel and at least part of said source and drain regions to form a gate for said element, and a region of material of said one conductivity type provided in the substrate contiguous with said channel, said region having an active impurity concentration higher than that of said substrate and a resistivity lower than that of said substrate.
Claim 2
Dependent Claim
123 words
A memory element comprising a conductive substrate of one conductivity type having first and second spaced apart regions of another conductivity forming a source and a drain for the element, respectively, said regions being interconnected by a thin region of said other conductivity type forming a channel between the source and drain; first and second insulating layers on the surface of said substrate overlying said channel and at least part of said source and drain regions to form a gate for said element, and a region of material of said one conductivity type provided in the substrate contiguous with said channel, said region having an active impurity concentration higher than that of said substrate and a resistivity lower than that of said substrate.
Claim 3
Dependent Claim
28 words
The memory element of claim 1 wherein said substrate is formed of P type material and wherein said source and drain regions are formed of N type material.
Claim 4
Dependent Claim
119 words
A memory element comprising a conductive substrate of one conductivity type having first and second spaced apart regions of another conductivity forming a source and a drain for the element, respectively, said regions being interconnected by a thin region of said other conductivity type forming a channel between the source and drain; insulation layer means formed on the surface of said substrate overlying said channel and at least part of said source and drain regions capable of storing charge, and a region of material of said one conductivity type provided in the substrate contiguous with said channel, said region having an active impurity concentration higher than that of said substrate and a resistivity lower than that of said substrate.
Claim 5
Dependent Claim
119 words
A memory element comprising a conductive substrate of one conductivity type having first and second spaced apart regions of another conductivity forming a source and a drain for the element, respectively, said regions being interconnected by a thin region of said other conductivity type forming a channel between the source and drain; insulation layer means formed on the surface of said substrate overlying said channel and at least part of said source and drain regions capable of storing charge, and a region of material of said one conductivity type provided in the substrate contiguous with said channel, said region having an active impurity concentration higher than that of said substrate and a resistivity lower than that of said substrate.
Claim 6
Dependent Claim
21 words
The memory element of claim 3 wherein said insulation mean forms part of the structure of a gate for said device.
Claim 7
Independent Claim
91 words
A device including a conductive substrate of one conductivity type having spaced apart source and drain regions of another conductivity type formed therein, said source and drain regions being interconnected by a channel of said other conductivity type; gate means for storing charge formed upon the surface of said substrate overlying said channel; and a region of material of said one conductivity type extending beneath said channel, contiguous therewith, said region having an active impurity concentration higher than that of said substrate and a resistivity lower than that of said substrate.
Claim 8
Independent Claim
91 words
A device including a conductive substrate of one conductivity type having spaced apart source and drain regions of another conductivity type formed therein, said source and drain regions being interconnected by a channel of said other conductivity type; gate means for storing charge formed upon the surface of said substrate overlying said channel; and a region of material of said one conductivity type extending beneath said channel, contiguous therewith, said region having an active impurity concentration higher than that of said substrate and a resistivity lower than that of said substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-04-11 | 1980-10-11 | 1981-04-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-04-11 | 1984-10-11 | 1985-04-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-04-11 | 1988-10-11 | 1989-04-12 | $7700.00 | Window Closed / Lapsed |