Memory circuit using variable threshold level field-effect device

Claim 2

A memory circuit comprising: A. a field-effect memory transistor having a gate input electrode and source and drain output electrodes, said memory transistor having a first threshold when subjected to a gate signal voltage less than a first value and having a second threshold when subjected to a gate signal voltage greater than a second value which is higher than said first value; B. first and second field-effect addressing transistors, each having a gate electrode, a source electrode, and a drain electrode, said source and drain electrodes of said memory transistor and said source and drain electrodes of said first and second addressing transistors being cOnnected in series with each other to permit current flow through said source and drain electrodes of said memory transistor only when both said addressing transistors are conductive; C. means for applying addressing signals to the gate electrodes of said addressing transistors so as to render the latter conductive; and D. means for applying a gate signal voltage to the gate of said memory transistor when said addressing transistors are conductive, said gate signal voltage being selectively less than said first value to cause said memory transistor to have said first threshold corresponding to a first binary number, greater than said second value to cause said memory transistor to have said second threshold corresponding to a second binary number, and greater than said first value and less than said second value to read the threshold of said memory transistor non-destructively.

Claim 3

The memory circuit of claim 1 in which said memory field-effect transistor is a metal-aluminum oxide-silicon dioxide-semi-conductor.

Claim 4

a first-coordinate address metal-insulator-silicon field-effect transistor comprising a gate electrode and source and drain electrodes, said source and drain electrodes of said first-coordinate address transistor being connected in series with the source and drain electrodes of said memory transistor of the respective cell to form a series circuit; B. a first first-coordinate address input terminal connected to the gate electrodes of said first-coordinate address transistors of said first and second one-bit cells; C. a second first-coordinate address input terminal connected to the gate electrodes of said first-coordinate address transistors of said third and fourth one-bit cells; D. a first second-coordinate address field-effect transistor having a gate electrode and further having source and drain electrodes connected in series with said series circuits of said first and third one-bit cells; E. a second second-coordinate address field-eFfect transistor having a gate electrode and further having source and drain electrodes connected in series with said series circuits of said second and fourth one-bit cells; F. a first second-coordinate address input terminal connected to said gate electrode of said first second-coordinate address transistor; G. a second second-coordinate address input terminal connected to said gate electrode of said second second-coordinate address transistor: and H. a common input terminal connected to the gate electrodes of all of said memory field-effect transistors for selectively receiving a gate signal voltage less than said first value, a gate signal voltage greater than said second value and a gate signal voltage which is between said first and second values.

Claim 5

a first-coordinate address metal-insulator-silicon field-effect transistor comprising a gate electrode and source and drain electrodes, said source and drain electrodes of said first-coordinate address transistor being connected in series with the source and drain electrodes of said memory transistor of the respective cell to form a series circuit; B. a first first-coordinate address input terminal connected to the gate electrodes of said first-coordinate address transistors of said first and second one-bit cells; C. a second first-coordinate address input terminal connected to the gate electrodes of said first-coordinate address transistors of said third and fourth one-bit cells; D. a first second-coordinate address field-effect transistor having a gate electrode and further having source and drain electrodes connected in series with said series circuits of said first and third one-bit cells; E. a second second-coordinate address field-eFfect transistor having a gate electrode and further having source and drain electrodes connected in series with said series circuits of said second and fourth one-bit cells; F. a first second-coordinate address input terminal connected to said gate electrode of said first second-coordinate address transistor; G. a second second-coordinate address input terminal connected to said gate electrode of said second second-coordinate address transistor: and H. a common input terminal connected to the gate electrodes of all of said memory field-effect transistors for selectively receiving a gate signal voltage less than said first value, a gate signal voltage greater than said second value and a gate signal voltage which is between said first and second values.

Claim 6

a first-coordinate address metal-insulator-silicon field-effect transistor comprising a gate electrode and source and drain electrodes connected in series with the drain electrode of said memory transistor; B. A first-coordinate address input terminal to the gate electrodes of said first-coordinate transistors of said first and second one-bit cells; C. A second first-coordinate address input terminal to the gate electrodes of said first-coordinate transistors of said third and fourth one-bit cells; D. A first second-coordinate address field-effect transistor having source and drain electrodes connected in series with said source electrodes of said memory transistors of said first and third one-bit cells; E. A second second-coordinate address field-effect transistor having source and drain electrodes connected in series with said source electrodes of said memory transistors of said second and fourth one-bit cells; F. A readout control terminal connected to said source electrodes of each of said second-coordinate address transistors; G. A first second-coordinate address input terminal to the gate of said first second-coordinate transistor; H. A second second-coordinate address input terminal to the gate of said second second-coordinate transistor; I. A first load element connected in series with said source and drain electrodes of said first-coordinate address transistor of said first and third one-bit cells; and J. A second load element connected in series with said source and drain electrodes of said first-coordinate address transistor of said second and fourth one-bit cells.

Claim 7

a first-coordinate address metal-insulator-silicon field-effect transistor comprising a gate electrode and source and drain electrodes connected in series with the drain electrode of said memory transistor; B. A first-coordinate address input terminal to the gate electrodes of said first-coordinate transistors of said first and second one-bit cells; C. A second first-coordinate address input terminal to the gate electrodes of said first-coordinate transistors of said third and fourth one-bit cells; D. A first second-coordinate address field-effect transistor having source and drain electrodes connected in series with said source electrodes of said memory transistors of said first and third one-bit cells; E. A second second-coordinate address field-effect transistor having source and drain electrodes connected in series with said source electrodes of said memory transistors of said second and fourth one-bit cells; F. A readout control terminal connected to said source electrodes of each of said second-coordinate address transistors; G. A first second-coordinate address input terminal to the gate of said first second-coordinate transistor; H. A second second-coordinate address input terminal to the gate of said second second-coordinate transistor; I. A first load element connected in series with said source and drain electrodes of said first-coordinate address transistor of said first and third one-bit cells; and J. A second load element connected in series with said source and drain electrodes of said first-coordinate address transistor of said second and fourth one-bit cells.

Claim 8

a first-coordinate address metal-insulator-silicon field-effect transistor having a gate electrode and source and drain electrodes, said source and drain electrodes of said first-coordinate address transistor being connected in series with the source and drain electrodes of said memory transistor of the respective cell to form a series circuit, and

Claim 9

a first-coordinate address metal-insulator-silicon field-effect transistor having a gate electrode and source and drain electrodes, said source and drain electrodes of said first-coordinate address transistor being connected in series with the source and drain electrodes of said memory transistor of the respective cell to form a series circuit, and

Claim 10

a load element connected to the drain electrode of the memory transistor of the respective cell; B. a first first-coordinate address input terminal connected to the gate electrodes of said first-coordinate address transistors of said first and second one-bit cells; C. a second first-coordinate address input terminal connected to the gate electrodes of said first-coordinate address transistors of said third and fourth one-bit cells; D. a first second-coordinate address field-effect transistor having a gate electrode and further having source and drain electrodes connected in series with said series circuits of said first and third one-bit cells; E. a second second-coordinate address field-effect transistor having a gate electrode and further having source and drain electrodes connected in series with said series circuits of said second and fourth one-bit cells; F. a first second-coordinate address input terminal connected to said gate electrode of said first second-coordinate address transistor; G. a second second-coordinate address input terminal connected to said gate electrode of said second second-coordinate address transistor; H. a common input terminal connected to the gate electrodes of all of said memory field-effect transistors; I. a first interconnecting field-effect transistor having a gate electrode and further having source and drain electrodes connected in series between said drain electrodes of said memory transistors of said first and third one-bit cells; J. a second interconnecting field-effect transistor having a gate electrode and further having source and drain electrodes connected in series between the drain electrodes of said memory transistors of said second and fourth one-bit cells, said gate electrodes of said first and second interconnecting field-effect transistors being connected together to make said interconnecting transistors conductive and nonconductive in unison; K. a first grounding field-effect transistor having a gate electrode and further having source and drain electrodes connected in series between a fixed potential and the drain electrode of said memory transistor of said first one-bit cell; and L. a second grounding field-effect transistor having a gate electrode and further having source and drain electrodes connected in series between said fixed potential and the drain electrode of said memory transistor of said second one-bit cell, said gate electrodes of said first and second grounding transistors being connected together to make said grounding transistors conductive and nonconductive in unison.

Claim 11

a load element connected to the drain electrode of the memory transistor of the respective cell; B. a first first-coordinate address input terminal connected to the gate electrodes of said first-coordinate address transistors of said first and second one-bit cells; C. a second first-coordinate address input terminal connected to the gate electrodes of said first-coordinate address transistors of said third and fourth one-bit cells; D. a first second-coordinate address field-effect transistor having a gate electrode and further having source and drain electrodes connected in series with said series circuits of said first and third one-bit cells; E. a second second-coordinate address field-effect transistor having a gate electrode and further having source and drain electrodes connected in series with said series circuits of said second and fourth one-bit cells; F. a first second-coordinate address input terminal connected to said gate electrode of said first second-coordinate address transistor; G. a second second-coordinate address input terminal connected to said gate electrode of said second second-coordinate address transistor; H. a common input terminal connected to the gate electrodes of all of said memory field-effect transistors; I. a first interconnecting field-effect transistor having a gate electrode and further having source and drain electrodes connected in series between said drain electrodes of said memory transistors of said first and third one-bit cells; J. a second interconnecting field-effect transistor having a gate electrode and further having source and drain electrodes connected in series between the drain electrodes of said memory transistors of said second and fourth one-bit cells, said gate electrodes of said first and second interconnecting field-effect transistors being connected together to make said interconnecting transistors conductive and nonconductive in unison; K. a first grounding field-effect transistor having a gate electrode and further having source and drain electrodes connected in series between a fixed potential and the drain electrode of said memory transistor of said first one-bit cell; and L. a second grounding field-effect transistor having a gate electrode and further having source and drain electrodes connected in series between said fixed potential and the drain electrode of said memory transistor of said second one-bit cell, said gate electrodes of said first and second grounding transistors being connected together to make said grounding transistors conductive and nonconductive in unison.

Claim 12

The memory circuit of claim 1 in which said memory field-effect transistor is a metal-silicon nitride-silicon dioxide semiconductor.

Claim 13

A memory circuit comprising: A. a matrix of first, second, third and fourth one-bit cells each including

Claim 14

A memory circuit comprising: A. a matrix of first, second, third and fourth one-bit cells each including

Claim 15

A memory circuit comprising: A. A matrix of first, second, third and fourth one-bit cells, each comprising:

Claim 16

A memory circuit comprising: A. A matrix of first, second, third and fourth one-bit cells, each comprising:

Claim 17

A memory circuit comprising: A. a matrix of first, second, third, and fourth one-bit cells, each comprising:

Claim 18

A memory circuit comprising: A. a matrix of first, second, third, and fourth one-bit cells, each comprising:

Claim 19

The memory circuit of claim 6, in which said first-coordinate address transistor of each said one-bit cells has its said source and drain electrodes connected in series between the source electrode of the memory trainsistor of respective cell and the drain electrode of the respective second-coordinate address transistor connected thereto.

Claim 20

The memory circuit of claim 7 in which each of said one-bit cells comprises, in addition, a pair of field-effect transistors having source and drain electrodes connected together and connected in series with the respective memory transistor of that cell, and said circuit comprises, in addition: A. A first field-effect load transistor connected in series with said pair of parallel-connected transistors of said first and third one-bit cells; and B. A second field-effect load transistor connected in series with the pair of parallel-connected transistors of said second and fourth one-bit cells.