Buried-strap formation in a dram trench capacitor

Claim 1

A method of fabricating an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, said trench storage capacitor including a trench formed in a substrate having a dopant which causes said substrate to be of a first conductivity, said trench being lined with a first semiconducting material having a dopant which causes said first semiconducting material to be of a second conductivity, said dopant of said second conductivity also being partially diffused into said substrate, and said trench also being lined thereafter with a layer of dielectric material and filled subsequently with a second semiconducting material having a dopant which causes said second semiconducting material to be one of said first and second conductivitites, said second semiconducting material being partially recessed within said trench said trench being, lined with an oxide collar after said recessing, and filled with a third semiconducting material which may be either doped or undoped, said method comprising the steps of: etching portions of said oxide collar and said third semiconducting material to re-open a portion of said trench; filling said portion of said trench with a single crystalline semiconducting material; and forming an active area of said access transistor on said substrate, said forming causing a selectively controlled outdifussion of a dopant along a path that extends through both said single crystalline semiconducting material and a selected portion of said substrate, said path being electrically conductive and operating to electrically connect said trench storage capacitor with said access transistor.

Claim 2

A method of fabricating an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, said trench storage capacitor including a trench formed in a substrate having a dopant which causes said substrate to be of a first conductivity, said trench being lined with a first semiconducting material having a dopant which causes said first semiconducting material to be of a second conductivity, said dopant of said second conductivity also being partially diffused into said substrate, and said trench also being lined thereafter with a layer of dielectric material and filled subsequently with a second semiconducting material having a dopant which causes said second semiconducting material to be one of said first and second conductivitites, said second semiconducting material being partially recessed within said trench said trench being, lined with an oxide collar after said recessing, and filled with a third semiconducting material which may be either doped or undoped, said method comprising the steps of: etching portions of said oxide collar and said third semiconducting material to re-open a portion of said trench; filling said portion of said trench with a single crystalline semiconducting material; and forming an active area of said access transistor on said substrate, said forming causing a selectively controlled outdifussion of a dopant along a path that extends through both said single crystalline semiconducting material and a selected portion of said substrate, said path being electrically conductive and operating to electrically connect said trench storage capacitor with said access transistor.

Claim 10

A method of fabricating an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell comprising the steps of: etching a trench into a substrate of a first semiconducting material, said first semiconducting material having a dopant which causes said semiconducting material to be of a first conductivity; lining said trench with a second semiconducting material having a dopant which causes said second semiconducting material to be of a second conductivity; partially diffusing said dopant which causes said second conductivity into said substrate; thereafter lining said trench with a layer of dielectric material; thereafter filling said trench with a third semiconducting material having a dopant which causes said third semiconducting material to be one of said first and second conductivities; etching portions of said layer of dielectric material and said third semiconducting material to re-open said trench; refilling said partially re-opened portion of said trench with an oxide; selectively etching said oxide to form a dielectric collar; refilling said trench with doped or undoped polysilicon; etching portions of said doped or undoped polysilicon layer and said dielectric collar to partially re-open said trench; growing a single crystalline layer from a sidewall of said trench; and forming an active area of said access transistor on said substrate, said forming causing a selectively controlled outdifussion of dopants present in said trench along a path that extends through both said single crystalline semiconducting material and a selected portion of said substrate, said path being electrically conductive and operating to electrically connect said trench storage capacitor with said access transistor.

Claim 11

A method of fabricating an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell comprising the steps of: etching a trench into a substrate of a first semiconducting material, said first semiconducting material having a dopant which causes said semiconducting material to be of a first conductivity; lining said trench with a second semiconducting material having a dopant which causes said second semiconducting material to be of a second conductivity; partially diffusing said dopant which causes said second conductivity into said substrate; thereafter lining said trench with a layer of dielectric material; thereafter filling said trench with a third semiconducting material having a dopant which causes said third semiconducting material to be one of said first and second conductivities; etching portions of said layer of dielectric material and said third semiconducting material to re-open said trench; refilling said partially re-opened portion of said trench with an oxide; selectively etching said oxide to form a dielectric collar; refilling said trench with doped or undoped polysilicon; etching portions of said doped or undoped polysilicon layer and said dielectric collar to partially re-open said trench; growing a single crystalline layer from a sidewall of said trench; and forming an active area of said access transistor on said substrate, said forming causing a selectively controlled outdifussion of dopants present in said trench along a path that extends through both said single crystalline semiconducting material and a selected portion of said substrate, said path being electrically conductive and operating to electrically connect said trench storage capacitor with said access transistor.

Claim 21

A method of fabricating DRAM cell having an access transistor and a trench capacitor disposed in a trench formed in a substrate, comprising: forming said trench capacitor, including a polysilicon storage plate disposed within said trench; thereafter forming a single crystalline silicon layer within said trench, said single crystalline silicon layer being disposed above said polysilicon storage plate; and subsequently permitting dopants within said trench to diffuse into said substrate through said single crystalline silicon layer to form an electrical connection between said trench capacitor and said access transistor.

Claim 22

A method of fabricating DRAM cell having an access transistor and a trench capacitor disposed in a trench formed in a substrate, comprising: forming said trench capacitor, including a polysilicon storage plate disposed within said trench; thereafter forming a single crystalline silicon layer within said trench, said single crystalline silicon layer being disposed above said polysilicon storage plate; and subsequently permitting dopants within said trench to diffuse into said substrate through said single crystalline silicon layer to form an electrical connection between said trench capacitor and said access transistor.