Apparatus and method for maintaining status flags and condition codes using a renaming technique in an out of order floating point execution unit

Claim 2

Apparatus for maintaining status flags and condition codes in a floating point unit (FPU) capable of out-of-order and speculative execution and including an instruction dispatch unit (IDU) and an instruction fetch unit (IFU) comprising; a) a floating point queue (FPQ) for receiving speculative in-order instructions and issuing out-of-order and/or speculative instructions containing a group identifier tag (GID) and a target identifier tag (TID), the GID tag indicating a set of instructions bounded at each end by an interruptible or branch instruction; the TID tag indicative of the identity of a targeted architected facility and the program order of the instruction; b) a floating point status and control register (FPSCR) containing status and control bits for each instruction, the FPSCR being updated when an instruction is executed and committed; c) a FPSCR renaming mechanism for assigning an FPSCR rename to selected FPSCR bits during instruction dispatch from the IFU to the FPQ when an arithmetic instruction is dispatched that has a GID which has not been committed by the IDU and does not already have an FPSCR rename assigned, as determined by the FPQ, the FPSCR rename mechanism utilizing the TID tag upon the presence of selected bits in the FPSCR; d) means for updating the FPSCR bits as a new arithmetic instruction enters the write-back stage in the FPU; e) means for merging the resulting FPSCR updates of all instructions in a given GID into one FPSCR rename register; and f) means for clearing an FPSCR rename upon i) the GID assigned to the rename being committed by the IDU; ii) all renames being cleared where the renames are newer or equal to an interrupt or branch re-direction point.

Claim 3

The apparatus of claim 1 further including means for merging a plurality of floating point unit (FPU) operation status bits into a common rename register entry.

Claim 4

The apparatus of claim 1 further including a floating point register (FPR) rename mechanism coupled to an instruction bus for receiving an input instruction and group identifier and target identifier (GID and TID) tags for each instruction, the floating point register (FPR) rename mechanism providing an input to the floating point queue (FPO) for implementing register renaming by expanding the number of architected floating point registers.

Claim 5

The apparatus of claim 1 wherein the floating point status and control register (FPSCR) rename mechanism includes a matrix in juxtaposition and coupled to a merged register renaming array.

Claim 6

The apparatus of claim 4 wherein the matrix array includes a plurality of columns and rows, selected columns and rows coupled together through logic elements for identifying (i) entries in the register rename array containing a matching group identifier tag (GID) or target identifier tag (TID), (ii) entries containing a matching GID being merged in a prioritized merge logic unit, and (iii) entries containing a matching TID being cleared.

Claim 7

The apparatus of claim 5 wherein the register array contains a number of registers equal to the number of outstanding group identifier (GID) tags supported in the processor, each register defining a plurality of fields in which bits are stored indicative of a valid bit; a rename assignment and merged status bits for an instruction.

Claim 8

The apparatus of claim 6 further including logic means for merging the outputs of the matrix and array columns to provide a merge floating point status and control register (FPSCR) data bus as an input to the register array and an updated status for an architected FPSCR.

Claim 9

In a floating point unit (FPU) capable of out of order and/or speculative instruction execution and including a floating point status and control register (FPSCR), a floating point queue (FPQ), and a FPSCR rename mechanism, a method for maintaining status flags and condition codes in the out-of-order floating point execution unit comprising the steps of: a) receiving in the floating point queue (FPQ) speculative in-order instructions and issuing out of order and speculative instructions containing a group identifier tag (GID) and a target identifier tag (TID), the GID tag indicating a set of instructions bounded at each end by an interruptible or branch instruction; the TID tag indicating the identity of a targeted architected facility and the program order of the instructions; b) loading a floating point status and control register (FPSCR) with status and control bits for each instruction, the (FPSCR) being updated when an instruction is executed and committed; c) assigning in the FPSCR renaming mechanism an FPSCR rename to selected FPSCR bits during instruction dispatch from an Instruction Fetch Unit (IFU) to the FPQ when an arithmetic instruction is dispatched that has a GID which has not been committed by an Instruction Dispatch Unit (IDU) and does not already have an FPSCR rename assigned, as determined by the floating point instruction queue (FPO); the FPSCR rename mechanism utilizing the TID tag upon the presence of selected bits in the FPSCR; d) updating the FPSCR bits in the FPSCR rename as a new arithmetic instruction enters the write-back stage in the FPU; e) merging the resulting FPSCR updates of all instructions in a given GID into one FPSCR rename register; and f) clearing an FPSCR rename upon i) the GID assigned to the rename being committed by the IDU; and ii) all renames being cleared where the renames are newer or equal to an interrupt or branch redirection point.

Claim 10

In a floating point unit (FPU) capable of out of order and/or speculative instruction execution and including a floating point status and control register (FPSCR), a floating point queue (FPQ), and a FPSCR rename mechanism, a method for maintaining status flags and condition codes in the out-of-order floating point execution unit comprising the steps of: a) receiving in the floating point queue (FPQ) speculative in-order instructions and issuing out of order and speculative instructions containing a group identifier tag (GID) and a target identifier tag (TID), the GID tag indicating a set of instructions bounded at each end by an interruptible or branch instruction; the TID tag indicating the identity of a targeted architected facility and the program order of the instructions; b) loading a floating point status and control register (FPSCR) with status and control bits for each instruction, the (FPSCR) being updated when an instruction is executed and committed; c) assigning in the FPSCR renaming mechanism an FPSCR rename to selected FPSCR bits during instruction dispatch from an Instruction Fetch Unit (IFU) to the FPQ when an arithmetic instruction is dispatched that has a GID which has not been committed by an Instruction Dispatch Unit (IDU) and does not already have an FPSCR rename assigned, as determined by the floating point instruction queue (FPO); the FPSCR rename mechanism utilizing the TID tag upon the presence of selected bits in the FPSCR; d) updating the FPSCR bits in the FPSCR rename as a new arithmetic instruction enters the write-back stage in the FPU; e) merging the resulting FPSCR updates of all instructions in a given GID into one FPSCR rename register; and f) clearing an FPSCR rename upon i) the GID assigned to the rename being committed by the IDU; and ii) all renames being cleared where the renames are newer or equal to an interrupt or branch redirection point.

Claim 11

In a floating point unit (FPU) capable of executing out of order/speculative instructions containing a group identifier tag (GID) and a target identifier tag (TID), the FPU including a floating point status and control register (FPSCR), a floating point queue (FPO) and an FPSCR rename mechanism, a method for maintaining status flags and condition codes in the FPSCR comprising the steps of: a) receiving an instruction including a TID/GID tag at the floating point queue; b) testing the instructions to determine if the GID has not been committed and the GID does not already have an FPSCR rename assigned; c) assigning an FPSCR rename in the event the conditions tested in step b are true; d) testing the floating point queue to determine if an instruction should be issued to a floating execution unit; e) a true condition initiating a test to determine if the arithmetic instruction has been executed and is in a write-back stage; f) comparing an instruction in write-back against a committing GID from an instruction dispatch unit or a previously committed GID; g) merging the instruction FPSCR data with an FPSCR rename entry containing the matching GID and merging with other execution unit FPSCR data if such data has a matching GID and updating the FPSCR rename entry; h) testing to determine if a branch or interrupt condition exists to redirect the process; i) a false condition initiating a test to determine if the FPSCR rename's GID has been committed by the instruction dispatch unit; and j) a true condition merging the FPSCR rename with other committing FPSCR rename entries and merging with one or both execution units FPSCR data if such entries have commit hit write-back and merging with the current architected FPSCR and updating the architected FPSCR and clearing the FPSCR rename entry containing the matching GID.

Claim 12

In a floating point unit (FPU) capable of executing out of order/speculative instructions containing a group identifier tag (GID) and a target identifier tag (TID), the FPU including a floating point status and control register (FPSCR), a floating point queue (FPO) and an FPSCR rename mechanism, a method for maintaining status flags and condition codes in the FPSCR comprising the steps of: a) receiving an instruction including a TID/GID tag at the floating point queue; b) testing the instructions to determine if the GID has not been committed and the GID does not already have an FPSCR rename assigned; c) assigning an FPSCR rename in the event the conditions tested in step b are true; d) testing the floating point queue to determine if an instruction should be issued to a floating execution unit; e) a true condition initiating a test to determine if the arithmetic instruction has been executed and is in a write-back stage; f) comparing an instruction in write-back against a committing GID from an instruction dispatch unit or a previously committed GID; g) merging the instruction FPSCR data with an FPSCR rename entry containing the matching GID and merging with other execution unit FPSCR data if such data has a matching GID and updating the FPSCR rename entry; h) testing to determine if a branch or interrupt condition exists to redirect the process; i) a false condition initiating a test to determine if the FPSCR rename's GID has been committed by the instruction dispatch unit; and j) a true condition merging the FPSCR rename with other committing FPSCR rename entries and merging with one or both execution units FPSCR data if such entries have commit hit write-back and merging with the current architected FPSCR and updating the architected FPSCR and clearing the FPSCR rename entry containing the matching GID.

Claim 13

An article of manufacturing, comprising: a computer usable medium having computer readable program code means in an out of order/floating point unit (FPU) comprising a floating point status and control register (FPSCR); a floating point queue (FPO) and a fpscr rename mechanism, the computer readable program code means in said article of manufacture comprising: (a) computer readable program code means for receiving in the floating point queue in order/speculative instructions and issuing out of order and speculative instructions containing a group identifier tag (GID) and a target identifier tag (TID), the group identifier tag indicating a set of instructions bounded at each end by an interruptible or branch instruction; the target identifier tag indicative of the identity of a targeted architected facility and the program order of the instructions; (b) computer readable program code means for loading the FPSCR with status and control bits for each instruction, the FPSCR being updated when an instruction is executed and committed; (c) computer readable program code means for assigning in the FPSCR renaming mechanism a floating point status and control register rename for selected floating point status and control bits during instruction dispatch from and an Instruction Fetch Unit (IFU) to the floating point queue (FPO) when an arithmetic instruction is dispatched and the instruction has a group identifier which has not been committed by an Instruction Dispatch Unit (IDU) and does not already have a FPSCR rename assigned as determined by the FPQ; the FPSCR rename mechanism utilizing the target identifier tag (TID) upon the presence of selected bits in the FPSCR; (d) computer readable program code means for updating the bits in the FPSCR rename as a new arithmetic instruction enters the write-back stage in the floating point unit; (e) computer readable program code means for merging the resulting FPSCR updates of all instructions in a given group identifier into one FPSCR rename; and (f) computer readable program code means for clearing a floating point status and control register rename register upon (i) the group identifier assigned to the rename being committed by the IDU and (ii) all renames being cleared where the renames are newer or equal to an interrupt or branch redirection point.

Claim 14

An article of manufacturing, comprising: a computer usable medium having computer readable program code means in an out of order/floating point unit (FPU) comprising a floating point status and control register (FPSCR); a floating point queue (FPO) and a fpscr rename mechanism, the computer readable program code means in said article of manufacture comprising: (a) computer readable program code means for receiving in the floating point queue in order/speculative instructions and issuing out of order and speculative instructions containing a group identifier tag (GID) and a target identifier tag (TID), the group identifier tag indicating a set of instructions bounded at each end by an interruptible or branch instruction; the target identifier tag indicative of the identity of a targeted architected facility and the program order of the instructions; (b) computer readable program code means for loading the FPSCR with status and control bits for each instruction, the FPSCR being updated when an instruction is executed and committed; (c) computer readable program code means for assigning in the FPSCR renaming mechanism a floating point status and control register rename for selected floating point status and control bits during instruction dispatch from and an Instruction Fetch Unit (IFU) to the floating point queue (FPO) when an arithmetic instruction is dispatched and the instruction has a group identifier which has not been committed by an Instruction Dispatch Unit (IDU) and does not already have a FPSCR rename assigned as determined by the FPQ; the FPSCR rename mechanism utilizing the target identifier tag (TID) upon the presence of selected bits in the FPSCR; (d) computer readable program code means for updating the bits in the FPSCR rename as a new arithmetic instruction enters the write-back stage in the floating point unit; (e) computer readable program code means for merging the resulting FPSCR updates of all instructions in a given group identifier into one FPSCR rename; and (f) computer readable program code means for clearing a floating point status and control register rename register upon (i) the group identifier assigned to the rename being committed by the IDU and (ii) all renames being cleared where the renames are newer or equal to an interrupt or branch redirection point.