US5630157A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Computer organization for multiple and out-of-order execution of condition code testing and setting instructions
Assignee: International Business Machines Corp
•
Filing: 1994-10-25
•
Granted: 1997-05-13
•
Expires: 2014-10-25
Abstract
Abstract Computer system with multiple, out-of-order, instruction issuing system suitable for superscalar processors with a RISC organization, also has a Fast Dispatch Stack (FDS), a dynamic instruction scheduling system that may issue multiple, out-of-order, instructions each cycle to functional units as dependencies allow. The basic issuing mechanism supports a short cycle time and its capabilities are augmented. Condition code dependent instructions issue in multiples and out-of-order. A fast register renaming scheme is presented. An instruction squashing technique enables fast precise interrupts and branch prediction. Instructions preceding and following one or more predicted conditional branch instructions may issue out-of-order and concurrently. The effects of executed instructions following an incorrectly predicted branch instruction or an instruction that causes a precise interrupt are undone in one machine cycle.
Inventors
- 👤 Harry Dwyer, III
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:29
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F9/30003; G06F9/30072; G06F9/3836; G06F9/3838; G06F9/384; G06F9/3854; G06F9/3856; G06F9/3858; G06F9/3861; G06F9/3863; F; F02; F02B; F02B75/00; F02B75/02; F02B2075/022; F02B2075/027; G06F11/00; G06F11/30; G06F11/34; G06F11/3457; G06F11/3461
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
135 words
A computer system unit comprising: bus means for providing a stream of instructions including condition code setting and condition code testing instructions; a buffer to store instructions until they are issued; scheduling and issuing unit means for scheduling and issuing multiple concurrent instructions, including condition code setting instructions and condition code testing instructions, which are out-of-order with respect to instruction stream order within a sufficiently short time so that the cycle time of said computer system unit is not limited by the operation time of the scheduling and issuing unit means; said scheduling and issuing unit means including means for binding a condition code testing instruction to an immediately preceding condition code setting instruction and preventing issue of a condition testing instruction until completion of the condition code setting instruction with which it is bound.
Claim 2
Dependent Claim
135 words
A computer system unit comprising: bus means for providing a stream of instructions including condition code setting and condition code testing instructions; a buffer to store instructions until they are issued; scheduling and issuing unit means for scheduling and issuing multiple concurrent instructions, including condition code setting instructions and condition code testing instructions, which are out-of-order with respect to instruction stream order within a sufficiently short time so that the cycle time of said computer system unit is not limited by the operation time of the scheduling and issuing unit means; said scheduling and issuing unit means including means for binding a condition code testing instruction to an immediately preceding condition code setting instruction and preventing issue of a condition testing instruction until completion of the condition code setting instruction with which it is bound.
Claim 3
Dependent Claim
176 words
A computer system unit, comprising: bus means for providing a stream of instructions including condition code setting and condition code testing instructions; a buffer to store instructions until they are issued; scheduling and issuing unit means for scheduling and issuing multiple concurrent instructions, including condition code setting instructions and condition code testing instructions, which are out-of-order with respect to instruction stream order within a sufficiently short time so that the cycle time of said computer system unit is not limited by the operation time of the scheduling and issuing unit means; said scheduling and issuinq unit means including means for binding a condition code testing instruction to an immediately precedinq condition code setting instruction and preventing issue of a condition testing instruction until completion of the condition code setting instruction with which it is bound; multiple condition code registers; means to attach a tag (CC -- tag) to a condition code setting instruction; and means for using such condition code setting instruction to address a specific condition code register when the condition code setting instruction executes.
Claim 4
Dependent Claim
176 words
A computer system unit, comprising: bus means for providing a stream of instructions including condition code setting and condition code testing instructions; a buffer to store instructions until they are issued; scheduling and issuing unit means for scheduling and issuing multiple concurrent instructions, including condition code setting instructions and condition code testing instructions, which are out-of-order with respect to instruction stream order within a sufficiently short time so that the cycle time of said computer system unit is not limited by the operation time of the scheduling and issuing unit means; said scheduling and issuinq unit means including means for binding a condition code testing instruction to an immediately precedinq condition code setting instruction and preventing issue of a condition testing instruction until completion of the condition code setting instruction with which it is bound; multiple condition code registers; means to attach a tag (CC -- tag) to a condition code setting instruction; and means for using such condition code setting instruction to address a specific condition code register when the condition code setting instruction executes.
Claim 5
Dependent Claim
47 words
The computer system unit of claim 1 further comprising: multiple condition code registers; and means for attaching a tag (CC -- tag) to a condition code testing instruction that matches a tag (CC -- tag) given to the condition code setting instruction whose code it must test.
Claim 6
Dependent Claim
183 words
A computer system unit, comprising: bus means for providing a stream of instructions including condition code setting and condition code testing instructions; a buffer to store instructions until they are issued; scheduling and issuing unit means for scheduling and issuing multiple concurrent instructions, including condition code setting instructions and condition code testing instructions, which are out-of-order with respect to instruction stream order within a sufficiently short time so that the cycle time of said computer system unit is not limited by the operation time of the scheduling and issuing unit means; said scheduling and issuing unit means including means for binding a condition code testing instruction to an immediately preceding condition code setting instruction and preventing issue of a condition testing instruction until completion of the condition code setting instruction with which it is bound; multiple condition code registers; means for preventing issuing of a condition code setting instruction or condition code testing instruction if an uncompleted preceding instruction in the scheduling and issuing unit has a tag which matches a tag of said condition code setting instruction or condition code testing instruction.
Claim 7
Dependent Claim
183 words
A computer system unit, comprising: bus means for providing a stream of instructions including condition code setting and condition code testing instructions; a buffer to store instructions until they are issued; scheduling and issuing unit means for scheduling and issuing multiple concurrent instructions, including condition code setting instructions and condition code testing instructions, which are out-of-order with respect to instruction stream order within a sufficiently short time so that the cycle time of said computer system unit is not limited by the operation time of the scheduling and issuing unit means; said scheduling and issuing unit means including means for binding a condition code testing instruction to an immediately preceding condition code setting instruction and preventing issue of a condition testing instruction until completion of the condition code setting instruction with which it is bound; multiple condition code registers; means for preventing issuing of a condition code setting instruction or condition code testing instruction if an uncompleted preceding instruction in the scheduling and issuing unit has a tag which matches a tag of said condition code setting instruction or condition code testing instruction.
Claim 8
Dependent Claim
38 words
The computer system unit of claim 1 further comprising: multiple condition code registers; and means for testing the code in the condition code register addressed by an attached condition code tag when a condition code testing instruction executes.
Claim 9
Dependent Claim
34 words
The computer system of claim 1 further including: an instruction cache; and issue generator means for allocating additional bits to instructions in an instruction stream to tag and assign vector bits to each instruction.
References Cited (Backward Citations)
US4293910A
Cited
US4498136A
Cited
US4654785A
Cited
US4807115A
Cited
US4760520A
Cited
US4722049A
Cited
US4853840A
Cited
US4991080A
Cited
US4903196A
Cited
US4942525A
Cited
US4833599A
Cited
US4920477A
Cited
US5179680A
Cited
US4991090A
Cited
EP0301220A2
Cited
US4901233A
Cited
US5228131A
Cited
EP0340453A2
Cited
US5003462A
Cited
US4991133A
Cited
US4972342A
Cited
EP0378830A2
Cited
US5142634A
Cited
EP0381471A2
Cited
US5226126A
Cited
US5072364A
Cited
US5075844A
Cited
US5136697A
Cited
US5197137A
Cited
US5471593A
Cited
US5185871A
Cited
US5185868A
Cited
US5226130A
Cited
US5201056A
Cited
US5197132A
Cited
US5283873A
Cited
US5265213A
Cited
US5257354A
Cited
US5287467A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-05-12 | 2000-11-11 | 2001-05-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-05-12 | 2004-11-11 | 2005-05-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-05-12 | 2008-11-11 | 2009-05-13 | $7700.00 | Window Closed / Lapsed |