RISC microprocessor architecture with multi-bit tag extended instructions for selectively attaching tag from either instruction or input data to arithmetic operation output

Claim 2

A microprocessor, comprising: a register file having a bi-directional port and first and second outputs and including a plurality of registers for storing data words therein, said data words including a full precision data portion and a tag field for identifying the data type thereof, wherein said first output provides separate data portion and tag field of a first data word and said second output provides a separate data portion and tag field of a second data word; first computing means having first and second inputs respectively coupled to said first and second outputs of said register file for performing arithmetic computation on said data portions of said first and second data words and providing a resulting data word having a data portion at a first output which is applied at said bi-directional port of said register file; a memory for storing a plurality of instruction words each having a full precision instruction portion and a tag field; an instruction register coupled to said memory for receiving an instruction word; and selector means for selecting between said tag field of said instruction word applied at a first input and said tag field of said first data word applied at a second input under control of predetermined bits from said tag field of said instruction word and providing at an output one of said tag fields applied at said first and second inputs, wherein said tag field provided at said output is applied at said bi-directional port of said register file and combined with said data portion of said resulting data word of said first computing means for storage into said register file.

Claim 3

The microprocessor of claim 1 further comprising second computing means responsive to said data portion and tag field of said first data word and said data portion and tag field of said second data word for performing floating point computation thereon and providing a resulting data word having a data portion and tag field at an output for storage into said register file.

Claim 4

The microprocessor of claim 2 wherein said first computing means further comprises a second output for providing an address word in response to instruction dependent computation of said data portions of said first and second data words.

Claim 5

The microprocessor of claim 3 further comprising a program counter coupled to said second output of said first computing means for storing said address word as a pointer to a memory location containing the next executable instruction.

Claim 6

The microprocessor of claim 1 wherein said tag field includes a first plurality of bits reserved for identifying said data type.

Claim 7

The microprocessor of claim 5 wherein said tag field further includes a second plurality of bits for instruction dependent control and a third plurality of bits reserved in the instruction word for selecting between the tag field of the instruction word and the tag field of one operand to provide the tag field for the data word resulting from instruction dependent computation of the operands.

Claim 8

The microprocessor architecture of claim 6 wherein said first plurality of bits reserved for identifying the data type includes: at least two bits for identifying one of a plurality of primary categories of data types; and at least two bits for identifying one of a plurality of subtype categories within each of said plurality of primary categories of data types.

Claim 9

The microprocessor architecture of claim 7 wherein said second plurality of bits for instruction dependent control includes at least first and second bits, wherein said first and second bits are set and tested independently for control of program execution branching based on the results thereof.

Claim 12

An integrated microprocessor having a reduced instruction set computer architecture, comprising: first means having a bi-directional port and first and second outputs and including a plurality of registers for storing data words therein, said data words including a full precision data portion and a tag field for identifying the data type thereof, wherein said first output provides a separate data portion and tag field of a first data word and said second output provides a separate data portion and tag field of a second data word; second means having first and second inputs respectively coupled to said first and second outputs of said first means for performing arithmetic computation on said data portions of said first and second data words and providing a resulting data word having a data portion at a first output which is applied at said bi-directional port of said first means; third means for storing a plurality of instruction words each having a full precision instruction portion and a tag field; fourth means coupled to said third means for receiving an instruction word; and fifth means for selecting between said tag field of said instruction word applied at a first input and said tag field of said first data word applied at a second input under control of predetermined bits from said tag field of said instruction word and providing at an output one of said tag fields applied at said first and second inputs, wherein said tag field provided at said output is applied at said bi-directional port of said first means and combined with said data portion of said resulting data word of said second means for storage into said first means.

Claim 13

An integrated microprocessor having a reduced instruction set computer architecture, comprising: first means having a bi-directional port and first and second outputs and including a plurality of registers for storing data words therein, said data words including a full precision data portion and a tag field for identifying the data type thereof, wherein said first output provides a separate data portion and tag field of a first data word and said second output provides a separate data portion and tag field of a second data word; second means having first and second inputs respectively coupled to said first and second outputs of said first means for performing arithmetic computation on said data portions of said first and second data words and providing a resulting data word having a data portion at a first output which is applied at said bi-directional port of said first means; third means for storing a plurality of instruction words each having a full precision instruction portion and a tag field; fourth means coupled to said third means for receiving an instruction word; and fifth means for selecting between said tag field of said instruction word applied at a first input and said tag field of said first data word applied at a second input under control of predetermined bits from said tag field of said instruction word and providing at an output one of said tag fields applied at said first and second inputs, wherein said tag field provided at said output is applied at said bi-directional port of said first means and combined with said data portion of said resulting data word of said second means for storage into said first means.

Claim 14

The microprocessor of claim 10 further comprising fifth means responsive to said data portion and tag field of said first data word and said data portion and tag field of said second data word for performing floating point computation thereon and providing a resulting data word having a data portion and tag field at an output for storage into said first means.

Claim 15

The microprocessor of claim 11 wherein said second means further comprises a second output for providing an address word in response to instruction dependent computation of said data portions of said first and second data words.

Claim 16

The microprocessor of claim 12 further comprising a program counter coupled to said second output of said second means for storing said address word as a pointer to a memory location containing the next executable instruction.