US4841436A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Tag Data processing apparatus for a data flow computer
Assignee: Mitsubishi Electric Corp
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Filing: 1986-05-30
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Granted: 1989-06-20
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Expires: 2006-05-30
Abstract
Abstract A tag data processing apparatus is described for use in a data flow computer utilizing a tagged token scheme. A tag adding process and tag restoring process are executed by using pipeline registers, a queue memory and simple control circuit, thereby obtaining high speed operation and superior throughput without the need for a tag memory table, complicated operation-test circuitry or a sequence control circuit.
Inventors
- 👤 Hajime Asano
- 👤 Hiroaki Terada
- 👤 Katsuhiko Asada
- 👤 Hiroaki Nishikawa
- 👤 Masahisa Shimizu
- 👤 Hiroki Miura
- 👤 Kenji Shima
- 👤 Shinji Komori
- 👤 Souichi Miyata
- 👤 Satoshi Matsumoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 22:05
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/44; G06F9/448; G06F9/4494
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
386 words
A tag data processing apparatus for a data flow computer wherein tag data, representing an identifier of the context of program execution, and operation instructions are carried on tokens moving in first in-first out queues, said tag data processing apparatus comprising: a plurality of serially connected pipeline registers for holding and transmitting tokens having tag data associated therewith, each pipeline register having an input end, an output end, and an enable lead, wherein said output end of a preceding pipeline register is connected to said input end of a succeeding pipeline register; queue memory means for storing usable tag data to be added to tokens having a tag add instruction and for storing tag data from tokens having a restore instruction, said queue memory means having a data input end operatively connected with said output ends of said pipeline registers, a data output end operatively connected with said input ends of said pipeline registers and having an enable lead; and control means, operatively connected to said pipeline registers, including: means for detecting that a token in one of said pipeline registers is a tagged token, and has one of a tag restoring instruction or a tag adding instruction; means for producing signals on said enable lead of said queue memory means for (a) writing the tag of a tagged token that is detected to have a tag restoring instruction to said queue memory means, and (b) writing a tag from said queue memory means to a tagged token which has a tag adding instruction, means for erasing said added tag from said queue memory means; and means for generating clock pulses for moving tokens through said pipeline registers; said control means causing said queue memory means to store said tags from said tagged token having a tag restoring instruction only when said token is detected to be tagged with said tag restoring instruction and said queue memory means is ready for input; said control means causing said tag to be erased from said queue memory means only when a particular condition is satisfied, and said control means causing said tag from the output of said queue memory means to be written to said token only when said token is determined to have a tag adding instruction and said queue memory means is ready to produce output.
Claim 2
Dependent Claim
386 words
A tag data processing apparatus for a data flow computer wherein tag data, representing an identifier of the context of program execution, and operation instructions are carried on tokens moving in first in-first out queues, said tag data processing apparatus comprising: a plurality of serially connected pipeline registers for holding and transmitting tokens having tag data associated therewith, each pipeline register having an input end, an output end, and an enable lead, wherein said output end of a preceding pipeline register is connected to said input end of a succeeding pipeline register; queue memory means for storing usable tag data to be added to tokens having a tag add instruction and for storing tag data from tokens having a restore instruction, said queue memory means having a data input end operatively connected with said output ends of said pipeline registers, a data output end operatively connected with said input ends of said pipeline registers and having an enable lead; and control means, operatively connected to said pipeline registers, including: means for detecting that a token in one of said pipeline registers is a tagged token, and has one of a tag restoring instruction or a tag adding instruction; means for producing signals on said enable lead of said queue memory means for (a) writing the tag of a tagged token that is detected to have a tag restoring instruction to said queue memory means, and (b) writing a tag from said queue memory means to a tagged token which has a tag adding instruction, means for erasing said added tag from said queue memory means; and means for generating clock pulses for moving tokens through said pipeline registers; said control means causing said queue memory means to store said tags from said tagged token having a tag restoring instruction only when said token is detected to be tagged with said tag restoring instruction and said queue memory means is ready for input; said control means causing said tag to be erased from said queue memory means only when a particular condition is satisfied, and said control means causing said tag from the output of said queue memory means to be written to said token only when said token is determined to have a tag adding instruction and said queue memory means is ready to produce output.
Claim 3
Dependent Claim
52 words
A tag data processing apparatus as in claim 1 wherein said control means generates a shift-in pulse for said writing the tag of a tagged token with a tag restoring instruction to the queue memory means, and generates a shift-out pulse for said erasing said added tag from the queue memory means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-19 | 1992-12-19 | 1993-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-19 | 1996-12-19 | 1997-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-19 | 2000-12-19 | 2001-06-20 | $7700.00 | Window Closed / Lapsed |