US4591979A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data-flow-type digital processing apparatus
Assignee: NEC Corp
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Filing: 1983-08-25
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Granted: 1986-05-27
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Expires: 2003-08-25
Abstract
Abstract A data processing apparatus having a dataflow architecture includes an addressor module, an operational module and a memory module, and data to be processed is accompanied by a command and is applied to the respective module through a uni-directional bus. The addressor module and the operational module are integrated within a common hardware circuit having a feedback loop. A normal operation (an arithmetic and logic operation) is executed by the common hardware circuit by using only the uni-directional bus, while an address generating operation is executed by the common hardware circuit by using the uni-directional bus and the feedback loop.
Inventors
- 👤 Masao Iwashita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 23:26
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/44; G06F9/448; G06F9/4494
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
313 words
A data flow-type digital processing apparatus comprising: an input latch including a first section storing a first data, a second section storing a second data, and a third section storing a designation code; a processing unit having a first input end, a second input end and an output end and adapted to execute an arithmetic operation and/or a logic operation using two input data which are supplied to said first and second input ends; an output latch including a section storing a result of the arithmetic operation and/or a logic operation of said processing unit; a multiplexer having a first input portion, a second input portion and an output portion and inserted between said input latch and said processing unit; a first bus coupling said first section of said input latch to said first input end of said processing unit; a second bus coupling said second section of said input latch to said first input portion of said multiplexer; a third bus coupling said output portion of said multiplexer to said second input end of said processing unit; a fourth bus coupling said output end of said processing unit to the storing section of said output latch; a fifth bus coupled to said output latch for deriving the result of the storing section of said output latch; a sixth bus coupling said output latch to said second input portion of said multiplexer to feed back the result of the storing section to said multiplexer; and, a control unit coupled to said input latch and said multiplexer for selectively applying a first signal and a second signal to said multiplexer according to said designation code stored in said third section of said input latch, said second bus being coupled to said third bus in response to said first signal, said sixth bus being coupled to said third bus in response to said second signal.
Claim 2
Dependent Claim
313 words
A data flow-type digital processing apparatus comprising: an input latch including a first section storing a first data, a second section storing a second data, and a third section storing a designation code; a processing unit having a first input end, a second input end and an output end and adapted to execute an arithmetic operation and/or a logic operation using two input data which are supplied to said first and second input ends; an output latch including a section storing a result of the arithmetic operation and/or a logic operation of said processing unit; a multiplexer having a first input portion, a second input portion and an output portion and inserted between said input latch and said processing unit; a first bus coupling said first section of said input latch to said first input end of said processing unit; a second bus coupling said second section of said input latch to said first input portion of said multiplexer; a third bus coupling said output portion of said multiplexer to said second input end of said processing unit; a fourth bus coupling said output end of said processing unit to the storing section of said output latch; a fifth bus coupled to said output latch for deriving the result of the storing section of said output latch; a sixth bus coupling said output latch to said second input portion of said multiplexer to feed back the result of the storing section to said multiplexer; and, a control unit coupled to said input latch and said multiplexer for selectively applying a first signal and a second signal to said multiplexer according to said designation code stored in said third section of said input latch, said second bus being coupled to said third bus in response to said first signal, said sixth bus being coupled to said third bus in response to said second signal.
Claim 3
Dependent Claim
51 words
A data flow-type digital processing apparatus as claimed in claim 1, in which said input latch further includes a fourth section storing an operation code designating a number of coupling of said sixth bus and said third bus, said second signal being applied to said multiplexer according to said operation code.
Claim 4
Dependent Claim
56 words
A data flow-type digital processing apparatus as claimed in claim 2, in which said control unit has a register storing said operation code, a counter counting a number of operation of said processing unit, and a comparator comparing said operation code of said register with a content of said counter for controlling the second signal application.
Claim 5
Dependent Claim
83 words
A data flow-type digital processing apparatus as claimed in claim 1, further comprising a queue memory coupled to said input latch for holding at least one input data having said first and second data and said designation code to be entered into said input latch during said processing unit executes the arithmetic operation and/or the logic operation of said first data stored in said first section of said input latch and a data fed back from said output latch through said sixth bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-26 | 1989-11-25 | 1990-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-26 | 1993-11-25 | 1994-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-26 | 1997-11-25 | 1998-05-27 | $7700.00 | Window Closed / Lapsed |