Memory address transformation system

Claim 2

Apparatus for transforming a set of input binary address signals into a plurality of sets of addresses for at least two pairs of memory modules, such that the aggregate of the module addresses spans the address capcity of the input address signals, comprising: A. an inverter, responsive to the input address signals, for generating the complement of the input address; B. a first subtracter, responsive to a set of input address signals and a set of signals representing the number of storage elements in a first memory module, for generating a first set of transformed address signals; C. a second subtracter, responsive to said inverter and a set of signals representing the number of storage elements in a second memory module, for generating a second set of transformed address signals; D. a first comparator, responsive to input address signals and a set of signals representing the number of storage elements in a first memory module, for generating a first selection signal indicating that the input address is greater than the capacity of the first memory module; E. a second comparator, responsive to said inverter and a set of signals representing the number of storage elemtns in a second memory module, for generating a second selector signal indicating that the complement of the input address is greater than the capacity of the second memory module; F. signals representing the number of storage elements in first and second pairs of memory modules including said first and second memory modules, for generating first and second sums representing the numbers of storage elements in said first and second and pairs of memory modules, respectively; G. a third comparator, responsive to the input address signals and said first adder for generating a selector signal representing whether or not the input address is greater than said first sum; H. a fourth comparator, responsive to the complemented input address signals and said second adder for generating a selector signal representing whether or not the complemented input address is greater than said second sum; I. a third subtracter, responsive to the set of input address signals and a set of signals representing the number of storage elements in said first pair of memory modules for generating a third set of transformed address signals. J. a multiplexer, receiving the sets of input address signals, complemented input address signals and said transformed address signals, for selecting the desired module address, in response to said selector signals from said comparators.

Claim 3

The apparatus of claim 1, further comprising: K. a set of buffers in said multiplexer for generating output signals suitable for connection off chip.

Claim 4

A memory system responsive to a set of input address signals comprising: A. a plurality of memory modules, each module having a source of signals representing the number of addressable memory cells contained therein; B. first and second adders, connected to first and second pairs of said memory modules, for generating the respective sums of the number of storage cells; C. an inverter, responsive to a set of input address signals, for generating the complement of the address; D. a first comparator, responsive to a first one of said memory modules and the input address signals for generating a plurality of intermediate carry signals and a carry-out signal; E. a second comparator, responsive to said first adder and the input address signals for generating a plurality of intermediate carry signals and a carry-out signal; F. third and fourth comparators, similarly responsive to said second adder and the last of said memory modules, respectively, together with the inverted input address signals, from said inverter, each comparator generating a plurality of intermediate carry signals and a carry-out signal; G. first, second and third subtracters, responsive to the first and last said memory modules and said first adder, respectively, together with said input address signals, for transforming the input address in accordance with the actual sizes of said memory modules whereby a complete set of storage locations is provided for the address span of the input address signals; H. multiplexer means receiving the input address signals, said inverter output and each of said subtracter outputs, and responsive to the carry-out signals from said comparators for selecting the desired output address.

Claim 5

A memory system responsive to a set of input address signals comprising: A. a plurality of memory modules, each module having a source of signals representing the number of addressable memory cells contained therein; B. first and second adders, connected to first and second pairs of said memory modules, for generating the respective sums of the number of storage cells; C. an inverter, responsive to a set of input address signals, for generating the complement of the address; D. a first comparator, responsive to a first one of said memory modules and the input address signals for generating a plurality of intermediate carry signals and a carry-out signal; E. a second comparator, responsive to said first adder and the input address signals for generating a plurality of intermediate carry signals and a carry-out signal; F. third and fourth comparators, similarly responsive to said second adder and the last of said memory modules, respectively, together with the inverted input address signals, from said inverter, each comparator generating a plurality of intermediate carry signals and a carry-out signal; G. first, second and third subtracters, responsive to the first and last said memory modules and said first adder, respectively, together with said input address signals, for transforming the input address in accordance with the actual sizes of said memory modules whereby a complete set of storage locations is provided for the address span of the input address signals; H. multiplexer means receiving the input address signals, said inverter output and each of said subtracter outputs, and responsive to the carry-out signals from said comparators for selecting the desired output address.

Claim 6

Address transformation apparatus responsive to input address signals comprising: A. first through fifth memory modules, each module having a set of addressable storage elements and a set of signals representing the number of storage elements therein; B. an inverter responsive to the input address signals for generating the complement of the input address signals; C. a first adder, responsive to the signals from said first and second memory modules for providing a first set of limit signals; D. a second adder, responsive to the fourth and fifth memory modules for providing a second set of limit signals; E. a first comparator, consisting of carry look-ahead logic, responsive to the input address signals and said first memory module size signals, and the input address signals for generating a plurality of intermediate carry signals and a carry-out signal for providing a set of intermediate carry signals and a carry-out signal; F. a second comparator, consisting of carry look-ahead logic, responsive to the input address signals and said first adder; G. a third comparator, responsive to the input address signals and said fifth memory module size signals, and the input address signals for generating a plurality of intermediate carry signals and a carry-out signal; H. a fourth comparator, responsive to the input address signals and said second adder, and the input address signals for generating a plurality of intermediate carry signals and a carry-out signal; I. a first substracter, responsive to the input address signals, said first comparator carry signals and said first memory module size signals for generating a first transformed address; J. a second subtracter, responsive to the input address signals, said third comparator carry signals and said fifth memory module size signals for generating a second transformed address; K. a third subtracter, responsive to the input address signals, said fourth comparator carry signals and said second adder for providing a third transformed address; L. a first selector responsive to said first and second comparator carry-out signals when the input address is not greater than said first module size and greater than said first module size but not greater than the sum of the first and second module sizes, respectively; M. a second selector responsive to said third and fourth comparator carry-out signals for generating fifth and fourth memory module selection signals when the complemented input address is not greater than said fifth module size and greater than said fifth module size but not greater than the sum of the fourth and fifth modules, respectively; N. a third selector, responsive to said second and fourth comparator carry-out signals for generating a third memory module select signal when the input address is greater than the sum of said first and second module sizes and the complemented input address is greater than the sum of said fourth and fifth module sizes; O. a multiplexer for gating the input address, one of said transformed addresses or the complemented input address in accordance with said memory mOdule select signals.

Claim 7

Address transformation apparatus responsive to input address signals comprising: A. first through fifth memory modules, each module having a set of addressable storage elements and a set of signals representing the number of storage elements therein; B. an inverter responsive to the input address signals for generating the complement of the input address signals; C. a first adder, responsive to the signals from said first and second memory modules for providing a first set of limit signals; D. a second adder, responsive to the fourth and fifth memory modules for providing a second set of limit signals; E. a first comparator, consisting of carry look-ahead logic, responsive to the input address signals and said first memory module size signals, and the input address signals for generating a plurality of intermediate carry signals and a carry-out signal for providing a set of intermediate carry signals and a carry-out signal; F. a second comparator, consisting of carry look-ahead logic, responsive to the input address signals and said first adder; G. a third comparator, responsive to the input address signals and said fifth memory module size signals, and the input address signals for generating a plurality of intermediate carry signals and a carry-out signal; H. a fourth comparator, responsive to the input address signals and said second adder, and the input address signals for generating a plurality of intermediate carry signals and a carry-out signal; I. a first substracter, responsive to the input address signals, said first comparator carry signals and said first memory module size signals for generating a first transformed address; J. a second subtracter, responsive to the input address signals, said third comparator carry signals and said fifth memory module size signals for generating a second transformed address; K. a third subtracter, responsive to the input address signals, said fourth comparator carry signals and said second adder for providing a third transformed address; L. a first selector responsive to said first and second comparator carry-out signals when the input address is not greater than said first module size and greater than said first module size but not greater than the sum of the first and second module sizes, respectively; M. a second selector responsive to said third and fourth comparator carry-out signals for generating fifth and fourth memory module selection signals when the complemented input address is not greater than said fifth module size and greater than said fifth module size but not greater than the sum of the fourth and fifth modules, respectively; N. a third selector, responsive to said second and fourth comparator carry-out signals for generating a third memory module select signal when the input address is greater than the sum of said first and second module sizes and the complemented input address is greater than the sum of said fourth and fifth module sizes; O. a multiplexer for gating the input address, one of said transformed addresses or the complemented input address in accordance with said memory mOdule select signals.