EP0340453A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Instruction handling sequence control system
Assignee: NEC Corp
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Filing: 1989-03-31
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Granted: —
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Expires: 2009-03-31
Abstract
Abstract The invention relates to an instruction handling sequence control system for use in a vector computer to issue and execute instructions without following the sequence of instruction execution designated by a program. The instruction handling sequence control system comprises first means (2) for holding a group of instructions to be issued to a vector operating unit (5) and a main storage handling unit (6); second means (3) for holding the states of the vector register, operating unit and main storage unit used under an instruction being executed; third means (7) for determining, out of the group of instructions held by the first means and on the basis of the states of the resources held by the second means, an instruction to be issued to the vector operating unit (5) and the main storage handling unit (6)without conforming to the programmed sequence of instruction issues.
Inventors
- 👤 Naoki C/O Nec Corporation Nishi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 07:40
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F15/8076; G06F15/8084; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3824; G06F9/3834; G06F9/3836; G06F9/3838
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
314 words
An instruction handling sequence control system for vector processing having a vector operating unit comprising at least one piplined arithmetic unit, a plurality of vector registers and a network combining said arithmetic unit and said vector registers, and a main storage handling unit for vector-based loading/storing between a main storage unit and said vector registers, further provided with: first means for holding a group of instructions to be issued to the vector operating unit and the main storage handling unit; second means for holding the states of the vector register, arithmetic unit and main storage unit used under an instruction being executed; and third means for determining, out of the group of instructions held by said first means and on the basis of the states of the resources held by said second means, an instruction to be issued to the vector operating unit and the main storage handling unit without conforming to the programmed sequence of instruction issues; wherein this third means has means for issuing, with respect to a vector store instruction in the group of instructions held by said first means and a vector load instruction in the group of instructions held by said first means, programmed to be issued after said vector store instruction, said vector load instruction before said vector store instruction to the vector operating unit and the main storage handling unit when the distance between vector elements designated by said vector store instruction is equal to that designated by said vector load instruction, the store starting point address designed by said vector store instruction is unequal to the load starting point address designated by said vector load instruction, and the difference between the store starting point address designated by said vector store instruction and the load starting point designated by said vector load instruction is smaller than the distance between vector elements designated by said vector load instruction.
Claim 2
Dependent Claim
314 words
An instruction handling sequence control system for vector processing having a vector operating unit comprising at least one piplined arithmetic unit, a plurality of vector registers and a network combining said arithmetic unit and said vector registers, and a main storage handling unit for vector-based loading/storing between a main storage unit and said vector registers, further provided with: first means for holding a group of instructions to be issued to the vector operating unit and the main storage handling unit; second means for holding the states of the vector register, arithmetic unit and main storage unit used under an instruction being executed; and third means for determining, out of the group of instructions held by said first means and on the basis of the states of the resources held by said second means, an instruction to be issued to the vector operating unit and the main storage handling unit without conforming to the programmed sequence of instruction issues; wherein this third means has means for issuing, with respect to a vector store instruction in the group of instructions held by said first means and a vector load instruction in the group of instructions held by said first means, programmed to be issued after said vector store instruction, said vector load instruction before said vector store instruction to the vector operating unit and the main storage handling unit when the distance between vector elements designated by said vector store instruction is equal to that designated by said vector load instruction, the store starting point address designed by said vector store instruction is unequal to the load starting point address designated by said vector load instruction, and the difference between the store starting point address designated by said vector store instruction and the load starting point designated by said vector load instruction is smaller than the distance between vector elements designated by said vector load instruction.
Claim 3
Dependent Claim
286 words
An instruction handling sequence control system for vector processing having a vector operating unit comprising at least one piplined arithmetic unit, a plurality of vector registers and a network combining said arithmetic unit and said vector registers, and a main storage handling unit for vector-based loading/storing between a main storage unit and said vector registers, further provided with: first means for holding a group of instructions to be issued to the vector operating unit and the main storage handling unit; second means for holding the states of the vector register, arithmetic unit and main storage unit used under an instruction being executed; and third means for determining, out of the group of instructions held by said first means and on the basis of the states of the resources held by said second means, an instruction to be issued to the vector operating unit and the main storage handling unit without conforming to the programmed sequence of instruction issues; wherein this third means has means for issuing, with respect to a vector store instruction in the group of instructions held by said first means and a vector load instruction in the group of instructions held by said first means, programmed to be issued after said vector store instruction, said vector load instruction before said vector store instruction to the vector operating unit and the main storage handling unit even when the continuous address range from the store starting point address, to be stored under said vector store instruction, to the final store address to be stored thereunder does not intersect the continuous address range from the load staring point address, to be loaded under said vector load instruction, to the final load address to be loaded thereunder.
Claim 4
Dependent Claim
286 words
An instruction handling sequence control system for vector processing having a vector operating unit comprising at least one piplined arithmetic unit, a plurality of vector registers and a network combining said arithmetic unit and said vector registers, and a main storage handling unit for vector-based loading/storing between a main storage unit and said vector registers, further provided with: first means for holding a group of instructions to be issued to the vector operating unit and the main storage handling unit; second means for holding the states of the vector register, arithmetic unit and main storage unit used under an instruction being executed; and third means for determining, out of the group of instructions held by said first means and on the basis of the states of the resources held by said second means, an instruction to be issued to the vector operating unit and the main storage handling unit without conforming to the programmed sequence of instruction issues; wherein this third means has means for issuing, with respect to a vector store instruction in the group of instructions held by said first means and a vector load instruction in the group of instructions held by said first means, programmed to be issued after said vector store instruction, said vector load instruction before said vector store instruction to the vector operating unit and the main storage handling unit even when the continuous address range from the store starting point address, to be stored under said vector store instruction, to the final store address to be stored thereunder does not intersect the continuous address range from the load staring point address, to be loaded under said vector load instruction, to the final load address to be loaded thereunder.
References Cited (Backward Citations)
No citation records indexed.
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