Patent US5825691A successfully refreshed from Google Patents.
US5825691A
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Circuit and method for terminating a write to a memory cell
Assignee: STMicroelectronics lnc USA
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Filing: 1997-05-19
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Granted: 1998-10-20
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Expires: 2017-05-19
Abstract
Abstract A start write sensing circuit for sensing a start of a write is coupled to a write simulation circuit. The write simulation circuit preferably includes a memory cell replicate to mimic the amount of time required for writing data to the memory cell. The state of the data stored in the memory cell replicate is changed upon the write sensing circuit sensing the start of a write. The memory cell replicate is preferably constructed using the same structure, design, and process as the memory cells of the array so as to accurately simulate the time required for writing data to a memory cell in the array. Upon the write to the memory cell replicate being completed, a write termination signal is generated for terminating the write signal. The write termination signal also is a reset signal for resetting circuits of the array to prepare for the next cycle, whether it be a read or a write.
Inventors
- 👤 David C. McClure
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:34
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C7/14
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
97 words
A circuit for generating a write termination signal, comprising: a start write sensing circuit for sensing the start of a write; a write termination signal generation circuit for generating a signal to terminate the write; and a timer circuit coupled to the start write sensing circuit and coupled to the write termination signal generation circuit, the timer circuit including a memory cell replicate having a pair of transistors of the same sizing and in the same circuit configuration as a memory cell in an array of memory cells; and a switching circuit coupled to the timer circuit.
Claim 2
Dependent Claim
97 words
A circuit for generating a write termination signal, comprising: a start write sensing circuit for sensing the start of a write; a write termination signal generation circuit for generating a signal to terminate the write; and a timer circuit coupled to the start write sensing circuit and coupled to the write termination signal generation circuit, the timer circuit including a memory cell replicate having a pair of transistors of the same sizing and in the same circuit configuration as a memory cell in an array of memory cells; and a switching circuit coupled to the timer circuit.
Claim 3
Dependent Claim
44 words
The circuit according to claim 1, further including: a state change generation circuit coupled to the start write sensing circuit for forcing a change in the state of the memory cell replicate upon the write to the memory cells in the array being sensed.
Claim 4
Dependent Claim
31 words
The circuit according to claim 2 wherein the switching circuit is coupled to the memory cell replicate to generate a switching circuit upon the state of the memory cell being changed.
Claim 5
Dependent Claim
18 words
The circuit according to claim 1, further including: a variable time control circuit coupled to the switching circuit.
Claim 6
Dependent Claim
43 words
The circuit according to claim 4 wherein the variable time control circuit includes a time advance circuit to advance the time for causing the write termination circuit to generate the write termination signal from a first selected time to a second selected time.
Claim 7
Dependent Claim
59 words
The circuit according to claim 5 wherein the time advance circuit includes a plurality of transistors having their gates coupled to a common switching node and their sources coupled to a first node and their drains coupled to a second node to cause the first and second nodes to be coupled together when the common switching node is enabled.
Claim 8
Dependent Claim
41 words
The circuit according to claim 6 wherein the number of transistors in the plurality is selected to increase the speed at which current flows from the first node to the second node to advance the second selected time a predetermined amount.
Claim 9
Dependent Claim
43 words
The circuit according to claim 7 wherein said first node is ground and the second node is a voltage value above ground before the common switching mode is enabled to connected the second node to ground when the common switching mode is enabled.
Claim 10
Dependent Claim
48 words
The circuit according to claim 4 wherein the variable time control circuit includes: a time delay circuit to delay the time for causing the write termination circuit or a second selected time or generate the write termination signal at a first selected time to a third selected time.
Claim 11
Dependent Claim
24 words
The circuit according to claim 9 wherein the time delay circuit includes: a plurality of delay gates to delay the output of the signal.
Claim 12
Dependent Claim
25 words
The circuit according to claim 10 wherein the number of delay gates in the plurality is selected to delay the output a selected time value.
Claim 13
Independent Claim
65 words
A method for generating a write termination signal, comprising: sensing the presentation of data for writing to a memory cell; simulating the time period required for storing the data in the memory cell; generating a write completion signal after the simulated time period has passed; and generating a write termination and reset signal a selected time period after the generation of the write completion signal.
Claim 14
Independent Claim
65 words
A method for generating a write termination signal, comprising: sensing the presentation of data for writing to a memory cell; simulating the time period required for storing the data in the memory cell; generating a write completion signal after the simulated time period has passed; and generating a write termination and reset signal a selected time period after the generation of the write completion signal.
Claim 15
Independent Claim
79 words
A method for generating a write termination signal, comprising: sensing the presentation of data for writing to a memory cell; storing a change of data state in a memory cell replicate to simulate the time required for writing data to a memory cell; generating a write completion signal after the data has changed state in the memory cell replicate; and generating a write termination and reset signal a selected time period after the generation of the write completion signal.
Claim 16
Independent Claim
79 words
A method for generating a write termination signal, comprising: sensing the presentation of data for writing to a memory cell; storing a change of data state in a memory cell replicate to simulate the time required for writing data to a memory cell; generating a write completion signal after the data has changed state in the memory cell replicate; and generating a write termination and reset signal a selected time period after the generation of the write completion signal.
Claim 17
Dependent Claim
49 words
The method according to claim 12, further including: simultaneously sensing the state of data on a write bus true and on a write bus complement; and generating the write start signal when the state of the data changes on either a write bus true or the write bus complement.
Claim 18
Dependent Claim
47 words
The method according to claim 12 wherein said step of simulating the time required for storing data in the memory cell comprises: writing new data to a memory cell replicate having the same electrical connection, device properties, and device sizing as the memory cell in the array.
Claim 19
Dependent Claim
35 words
The method according to claim 12, further including disabling a word line selection circuit to a memory array comprised of memory cells and resetting a read/write control circuit under the control of the reset signal.
Claim 20
Dependent Claim
123 words
A computer system for determining the length of a write cycle comprising: a microprocessor system; a memory device electrically connected to the microprocessor system and performing a write operation under instructions from the microprocessor; a start write sensing circuit within the memory device for sensing when data is provided from the microprocessor to the memory device for writing to the memory device; a write time duration circuit coupled to the start write sensing circuit and generating a write completed signal, a selected time after a start write signal is generated by the start write sensing circuit; and a write termination and reset circuit connected to the write simulation circuit for generating a signal to disable access of write data to the memory array.
Claim 21
Dependent Claim
123 words
A computer system for determining the length of a write cycle comprising: a microprocessor system; a memory device electrically connected to the microprocessor system and performing a write operation under instructions from the microprocessor; a start write sensing circuit within the memory device for sensing when data is provided from the microprocessor to the memory device for writing to the memory device; a write time duration circuit coupled to the start write sensing circuit and generating a write completed signal, a selected time after a start write signal is generated by the start write sensing circuit; and a write termination and reset circuit connected to the write simulation circuit for generating a signal to disable access of write data to the memory array.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-19 | 2002-04-20 | 2002-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-19 | 2006-04-20 | 2006-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-19 | 2010-04-20 | 2010-10-20 | $7700.00 | Window Closed / Lapsed |