Read/write memory having an improved write driver

Claim 2

A semiconductor memory, comprising: a plurality of memory cells arranged in rows and columns; a plurality of bit line pairs, each bit line pair associated with a column, for communicating a differential signal to and from a selected memory cell in its associated column; a write driver, for driving first and second input/output lines with a differential signal in a write operation; means for connecting a selected column to said first and second input/output lines respective to a column address; and first and second source follower transistors, each having its drain coupled to a power supply node, said first source follower transistor having its source coupled to said first input/output line, and said second source follower transistor having its source coupled to said second input/output line, each of said first and second source follower transistors having a gate controlled by said write driver in such a manner that said first and second source follower transistors have their gate biased to a voltage substantially that of their drain during a read operation; and wherein the gates of said source follower transistors are controlled by said write driver in such a manner that, during a write operation, the one of the first and second source follower transistors associated with the input/output line being driven to a level corresponding to the voltage of the power supply node has its gate biased to a voltage substantially that of its drain.

Claim 3

The memory of claim 1, further comprising: means for precharging said plurality of bit lines to a voltage substantially that of said power supply node.

Claim 4

The memory of claim 1, wherein said means for connecting comprises: a column decoder, having an input for receiving said column address, and having a plurality of outputs for selecting a column responsive to the value of said column address; and a plurality of pass gates, each having their conduction path coupled between an associated bit line and one of said input/output lines, and each having a control terminal controlled by an output of said column decoder, such that the pass gates associated with the selected column are conductive.

Claim 5

The memory of claim 3, further comprising: means for precharging said plurality of bit lines to a voltage substantially that of said power supply node.

Claim 6

The memory of claim 4, further comprising means for equilibrating the voltage of the bit lines in each pair with one another.

Claim 7

The memory of claim 5, wherein said means for precharging comprises a plurality of precharge transistors, each having a conduction path coupled between an associated bit line and said power supply node, and each having a control terminal controlled in such a manner that said precharge transistors are each conductive for a period of time in each cycle.

Claim 8

The memory of claim 6, wherein said control terminals of said plurality of precharge transistors are coupled to the outputs of said column decoder, so that each of said precharge transistors associated with a column not selected by said column decoder are conductive.

Claim 9

The memory of claim 1, wherein the gates of said source follower transistors are controlled by said write driver in such a manner that, during a write operation, the one of the first and second source follower transistors associated with the input/output line being driven to a level complementary to that corresponding to the voltage at said power supply node is turned off.

Claim 10

The memory of claim 8, wherein the gates of said source follower transistors are also controlled by said write driver in such a manner that the gates of both of said first and second source follower transistors are biased to their drain voltage upon the completion of said write operation.

Claim 11

A semiconductor memory comprising: a plurality of memory cells arranged in rows and columns; a plurality of bit line pairs, each bit line pair associated with a column, for communicating a differential signal to and from a selected memory cell in its associated column; a write driver, for driving first and second input/output lines with a differential signal in a write operation, comprising: a first driver having an input, and having an output coupled to said first input/output line; a second driver having an input, and having an output coupled to said second input/output line; and a data input for receiving input data, and for communicating complementary data states to the inputs of said first and second drivers; means for connecting a selected column to said first and second input/output lines responsive to a column address; and first and second source follower transistors, each having its drain coupled to a power supply node, said first source follower transistor having its source coupled to said first input/output line, and said second source follower transistor having its source coupled to said second input/output line, each of said first and second source follower transistors having a control terminal controlled by said write driver in such a manner that said first and second source follower transistors have their gates biased to a voltage substantially that at their drains during a read operation; wherein the gates of said source follower transistors are controlled by said write driver in such a manner that the source follower transistor associated with the input/output line being driven low during a write operation is turned off; wherein the voltage at said power supply node corresponds to a high logic level; and wherein the gates of said first and second source follower transistors are coupled to the inputs of said first and second drivers in such a manner that the first source follower transistor is turned off when said first driver is driving said first input/output line to a low logic level, and in such a manner that the second source follower transistor is turned off when said second driver is driving said second input/output line to a low logic level.

Claim 12

A semiconductor memory comprising: a plurality of memory cells arranged in rows and columns; a plurality of bit line pairs, each bit line pair associated with a column, for communicating a differential signal to and from a selected memory cell in its associated column; a write driver, for driving first and second input/output lines with a differential signal in a write operation, comprising: a first driver having an input, and having an output coupled to said first input/output line; a second driver having an input, and having an output coupled to said second input/output line; and a data input for receiving input data, and for communicating complementary data states to the inputs of said first and second drivers; means for connecting a selected column to said first and second input/output lines responsive to a column address; and first and second source follower transistors, each having its drain coupled to a power supply node, said first source follower transistor having its source coupled to said first input/output line, and said second source follower transistor having its source coupled to said second input/output line, each of said first and second source follower transistors having a control terminal controlled by said write driver in such a manner that said first and second source follower transistors have their gates biased to a voltage substantially that at their drains during a read operation; wherein the gates of said source follower transistors are controlled by said write driver in such a manner that the source follower transistor associated with the input/output line being driven low during a write operation is turned off; wherein the voltage at said power supply node corresponds to a high logic level; and wherein the gates of said first and second source follower transistors are coupled to the inputs of said first and second drivers in such a manner that the first source follower transistor is turned off when said first driver is driving said first input/output line to a low logic level, and in such a manner that the second source follower transistor is turned off when said second driver is driving said second input/output line to a low logic level.

Claim 13

The memory of claim 10, wherein said write driver further comprises: control circuitry, having an input for receiving a write control signal, and having outputs connected to the inputs of said first and second drivers and to the gates of said first and second source follower transistors, said control circuitry for placing said first and second drivers in a high impedance output condition, and for biasing the gates of said first and second source follower transistors to their drain voltages, responsive to said write control signal indicating the absence of a write operation.

Claim 18

The method of claim 12, further comprising: precharging said differential bit lines to a voltage substantially the same as the voltage of said power supply, upon completion of said write operation.

Claim 19

The method of claim 14, further comprising: after said biasing step, selecting a memory cell to be read by connecting said memory cell to the bit lines of its associated column and by connecting the bit lines of the selected column to said first and second input/output lines.

Claim 20

The method of claim 15, wherein said step of connecting the bit lines of the selected column to said first and second input/output lines is performed during said biasing step.

Claim 21

The method of claim 16, further comprising: sensing the differential signal on said first and second input/output lines.

Claim 22

The method of claim 12, further comprising: precharging said first and second input/output lines to a voltage substantially at the voltage of said power supply node, after said biasing step has begun.

Claim 23

The method of claim 18, further comprising: equilibrating said first and second input/output lines during said precharging step.