Patent US2161732A successfully refreshed from Google Patents.
Patent US5821910A successfully refreshed from Google Patents.
US5821910A
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Clock generation circuit for a display controller having a fine tuneable frame rate
Assignee: National Semiconductor Corp
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Filing: 1995-05-26
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Granted: 1998-10-13
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Expires: 2015-05-26
Abstract
Abstract A clock generation circuit for a display controller includes an intermediate dot clock generation circuit which receives an input clock signal and in response thereto generates an intermediate dot clock signal having a plurality of dot clock pulses. A row pulse generation circuit is coupled to the intermediate dot clock generation circuit and counts the intermediate dot clock signal dot clock pulses and generates a row pulse after a predetermined number of dot clock pulses and a programmable offset time. The row pulse generation circuit also generates a final dot clock signal by masking the intermediate dot clock signal with the programmable offset time after the predetermined number of dot clock pulses. A method of adjusting a rate at which data is transferred to a display screen is also disclosed.
Inventors
- 👤 Michael John Shay
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 12:34
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/18
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
175 words
A clock generation circuit for a display controller, comprising: an intermediate dot clock generation circuit which receives an input clock signal and in response thereto generates an intermediate dot clock signal having a plurality of dot clock pulses; and a row pulse generation circuit coupled to the intermediate dot clock generation circuit and configured to generate a final dot clock signal which clocks display data into a display, wherein the row pulse generation circuit generates the final dot clock signal by counting the intermediate dot clock signal dot clock pulses and masking the intermediate dot clock signal with a programmable offset time after a predetermined number of dot clock pulses; the row pulse generation circuit further configured to generate a row pulse to indicate that a full row of display data has been sent to the display, wherein the row pulse generation circuit generates the row pulse after the predetermined number of dot clock pulses and the programmable offset time; wherein a frame rate for the display is adjusted by adjusting the programmable offset time.
Claim 2
Dependent Claim
175 words
A clock generation circuit for a display controller, comprising: an intermediate dot clock generation circuit which receives an input clock signal and in response thereto generates an intermediate dot clock signal having a plurality of dot clock pulses; and a row pulse generation circuit coupled to the intermediate dot clock generation circuit and configured to generate a final dot clock signal which clocks display data into a display, wherein the row pulse generation circuit generates the final dot clock signal by counting the intermediate dot clock signal dot clock pulses and masking the intermediate dot clock signal with a programmable offset time after a predetermined number of dot clock pulses; the row pulse generation circuit further configured to generate a row pulse to indicate that a full row of display data has been sent to the display, wherein the row pulse generation circuit generates the row pulse after the predetermined number of dot clock pulses and the programmable offset time; wherein a frame rate for the display is adjusted by adjusting the programmable offset time.
Claim 3
Dependent Claim
73 words
A clock generation circuit in accordance with claim 1, wherein the intermediate dot clock generation circuit comprises: a binary clock division circuit coupled to receive the input clock signal and which performs binary clock division thereon to generate an output binary clock divided signal; and an integer clock division circuit coupled to receive the output binary clock divided signal and which performs integer clock division thereon to generate the intermediate dot clock signal.
Claim 4
Dependent Claim
26 words
A clock generation circuit in accordance with claim 1, further comprising: a configuration register coupled to the row pulse generation circuit for programming the offset time.
Claim 5
Dependent Claim
206 words
A clock generation circuit for a display controller, comprising: a binary clock division circuit which receives an input clock signal and which performs binary clock division thereon to generate an output binary clock divided signal; an integer clock division circuit coupled to receive the output binary clock divided signal and which performs integer clock division thereon to generate an intermediate dot clock signal having a plurality of dot clock pulses; and an offset clock generation circuit coupled to the integer clock division circuit and configured to generate a final dot clock signal which clocks display data into a display, wherein the offset clock generation circuit generates the final dot clock signal by counting the intermediate dot clock signal dot clock pulses and masking the intermediate dot clock signal with a programmable offset time after a predetermined number of dot clock pulses; the offset clock generation circuit further configured to generate a row pulse to indicate that a full row of display data has been sent to the display, wherein the offset clock generation circuit generates the row pulse after the predetermined number of dot clock pulses and the programmable offset time; wherein a frame rate for the display is adjusted by adjusting the programmable offset time.
Claim 6
Dependent Claim
206 words
A clock generation circuit for a display controller, comprising: a binary clock division circuit which receives an input clock signal and which performs binary clock division thereon to generate an output binary clock divided signal; an integer clock division circuit coupled to receive the output binary clock divided signal and which performs integer clock division thereon to generate an intermediate dot clock signal having a plurality of dot clock pulses; and an offset clock generation circuit coupled to the integer clock division circuit and configured to generate a final dot clock signal which clocks display data into a display, wherein the offset clock generation circuit generates the final dot clock signal by counting the intermediate dot clock signal dot clock pulses and masking the intermediate dot clock signal with a programmable offset time after a predetermined number of dot clock pulses; the offset clock generation circuit further configured to generate a row pulse to indicate that a full row of display data has been sent to the display, wherein the offset clock generation circuit generates the row pulse after the predetermined number of dot clock pulses and the programmable offset time; wherein a frame rate for the display is adjusted by adjusting the programmable offset time.
Claim 7
Dependent Claim
32 words
A clock generation circuit in accordance with claim 4, wherein the offset clock generation circuit also generates a frame pulse to indicate that a predetermined number of row pulses have been generated.
Claim 8
Independent Claim
159 words
A method of adjusting a rate at which data is transferred to a display screen, comprising the steps of: setting a programmable offset time; performing binary clock division on an input clock signal to generate an output binary clock divided signal; performing integer clock division on the output binary clock divided signal to generate an intermediate dot clock signal having a plurality of dot clock pulses; counting the intermediate dot clock signal dot clock pulses; masking the intermediate dot clock signal with the programmable offset time after a predetermined number of dot clock pulses to generate a final dot clock signal; clocking display data into a display with the final dot clock signal; generating a row pulse to indicate that a full row of display data has been sent to the display after the programmable number of dot clock pulses and the predetermined offset time; and adjusting the programmable offset time to adjust a frame rate for the display.
Claim 9
Independent Claim
159 words
A method of adjusting a rate at which data is transferred to a display screen, comprising the steps of: setting a programmable offset time; performing binary clock division on an input clock signal to generate an output binary clock divided signal; performing integer clock division on the output binary clock divided signal to generate an intermediate dot clock signal having a plurality of dot clock pulses; counting the intermediate dot clock signal dot clock pulses; masking the intermediate dot clock signal with the programmable offset time after a predetermined number of dot clock pulses to generate a final dot clock signal; clocking display data into a display with the final dot clock signal; generating a row pulse to indicate that a full row of display data has been sent to the display after the programmable number of dot clock pulses and the predetermined offset time; and adjusting the programmable offset time to adjust a frame rate for the display.
Claim 10
Dependent Claim
28 words
A method in accordance with claim 6, further comprising the step of: generating a frame pulse to indicate that a predetermined number of row pulses have been generated.
References Cited (Backward Citations)
US3873815A
Cited
US4287805A
Cited
WO1984000236A1
Cited
US4642794A
Cited
US4642789A
Cited
US4799053A
Cited
US5172108A
Cited
US4942553A
Cited
US5196839A
Cited
US5027330A
Cited
US5206635A
Cited
US5185602A
Cited
WO1990012388A1
Cited
EP0393487A2
Cited
US5408626A
Cited
US5204953A
Cited
US5084841A
Cited
US5254981A
Cited
US5430838A
Cited
US5278956A
Cited
US5187578A
Cited
US5259006A
Cited
US5293468A
Cited
EP0507571A2
Cited
WO1992020061A1
Cited
US5617118A
Cited
US5307056A
Cited
US5189319A
Cited
EP0552506A1
Cited
US5389948A
Cited
US5254888A
Cited
US5379339A
Cited
US5335322A
Cited
US5557733A
Cited
JPH0720833A
Cited
US5581280A
Cited
US5530458A
Cited
US5537128A
Cited
US5534889A
Cited
JPH07178972A
Cited
US5404473A
Cited
US5506809A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-12 | 2002-04-13 | 2002-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-12 | 2006-04-13 | 2006-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-12 | 2010-04-13 | 2010-10-13 | $7700.00 | Window Closed / Lapsed |