US5204953A
Expired / Lapsed
US
⏱️ 0.0 years remaining
One clock address pipelining in segmentation unit
Assignee: Intel Corp
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Filing: 1989-08-04
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Granted: 1993-04-20
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Expires: 2009-08-04
Abstract
Abstract A microprocessor which comprises a three input adder, a two input adder, apparatus for providing the components of a virtual address to the first and second adders on a first clock period, and apparatus for providing a segment base address to the first adder on the first clock period, apparatus for determining the type of addresses generated by the adders on a second clock period and for generating an output address on the second clock period, and apparatus for determining access violations during a third clock period.
Inventors
- 👤 Ashish Dixit
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:47
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/342; G06F12/00; G06F12/14; G06F12/1416; G06F12/1425; G06F12/1441
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
226 words
A microprocessor circuit for providing an address for each execution stage in a pipelined addressing system having pipelined stages for each instruction including a first decode stage, a second decode stage, a third execution stage, and a fourth writeback stage, said microprocessor circuit comprising first signal providing means for providing signals representing a displacement, a relative base address, and an index during said first decode stage; a combining means for combining the signals representing the displacement, the relative base address, and the index to provide an effective address during said second decode stage, said combining means coupled to said first signal providing means; second signal providing means for providing signals representing a segment base address during said first decode stage; a three input adder for combining the signals representing the displacement, the relative base address, the index, and the segment base address to provide a linear address during said second decode stage comprised of and three input adder, said three input adder coupled to said first signal providing means and said second signal providing means; means for providing the output of the combining means to an input of the three input adder; and third signal providing means for providing said effective address and said linear address during said third execution stage, said third signal providing means coupled to said combining means and said three input adder.
Claim 2
Dependent Claim
226 words
A microprocessor circuit for providing an address for each execution stage in a pipelined addressing system having pipelined stages for each instruction including a first decode stage, a second decode stage, a third execution stage, and a fourth writeback stage, said microprocessor circuit comprising first signal providing means for providing signals representing a displacement, a relative base address, and an index during said first decode stage; a combining means for combining the signals representing the displacement, the relative base address, and the index to provide an effective address during said second decode stage, said combining means coupled to said first signal providing means; second signal providing means for providing signals representing a segment base address during said first decode stage; a three input adder for combining the signals representing the displacement, the relative base address, the index, and the segment base address to provide a linear address during said second decode stage comprised of and three input adder, said three input adder coupled to said first signal providing means and said second signal providing means; means for providing the output of the combining means to an input of the three input adder; and third signal providing means for providing said effective address and said linear address during said third execution stage, said third signal providing means coupled to said combining means and said three input adder.
References Cited (Backward Citations)
US4783757A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-19 | 1996-10-19 | 1997-04-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-19 | 2000-10-19 | 2001-04-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-19 | 2004-10-19 | 2005-04-20 | $7700.00 | Window Closed / Lapsed |