Patent US5821804A successfully refreshed from Google Patents.
US5821804A
Expired / Lapsed
US
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Integrated semiconductor circuit
Assignee: Polaris Innovations Ltd
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Filing: 1996-04-08
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Granted: 1998-10-13
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Expires: 2016-04-08
Abstract
Abstract An integrated semiconductor circuit includes a semiconductor substrate. A number of first potential buses carry a first supply potential of the semiconductor circuit during operation. A number of second potential buses carry a second supply potential of the semiconductor circuit during operation. A number of circuit portions formed on the substrate are each connected between one of the first and one of the second potential buses for being supplied with electrical voltage. Connection points are formed on the substrate and are each assigned to one of the circuit portions for receiving an input or output signal for the circuit portion during operation of the circuit portion. Protective circuits are formed on the substrate and are each assigned to one of the circuit portions for preventing overvoltage. The protective circuits each have an input side connected to one of the connection points and an output side connected to the circuit portion. A common potential bus bar carries a reference potential being common with respect to all of the connection points during operation. The protective circuits have discharge paths coupled with the potential bus bar for dissipating overvoltages.
Inventors
- 👤 Wolfgang Nikutta
- 👤 Werner Reczek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 10:10
CPC Classifications
H; H10; H10D; H10D84/00; H10D89/00; H10D89/60; H10D89/601
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
208 words
An integrated semiconductor circuit, comprising: a semiconductor substrate; a number of first potential buses carrying a first supply potential of the semiconductor circuit during operation; a number of second potential buses carrying a second supply potential of the semiconductor circuit during operation; a number of circuit portions being formed on said semiconductor substrate and each being connected between a respective one of said first and a respective one of said second potential buses for being supplied with electrical voltage; connection points being formed on said semiconductor substrate and each being assigned to a respective one of said circuit portions for receiving an input or output signal for said respective circuit portion during operation of said circuit portion; protective circuits being formed on said semiconductor substrate and each being assigned to a respective one of said circuit portions for preventing overvoltage, said protective circuits each having an input side being connected to a respective one of said connection points and an output side being connected to said respective circuit portion; and a common potential bus bar carrying a reference potential being common with respect to all of said connection points during operation; said protective circuits having discharge paths being coupled with said common potential bus bar for dissipating overvoltages.
Claim 2
Dependent Claim
208 words
An integrated semiconductor circuit, comprising: a semiconductor substrate; a number of first potential buses carrying a first supply potential of the semiconductor circuit during operation; a number of second potential buses carrying a second supply potential of the semiconductor circuit during operation; a number of circuit portions being formed on said semiconductor substrate and each being connected between a respective one of said first and a respective one of said second potential buses for being supplied with electrical voltage; connection points being formed on said semiconductor substrate and each being assigned to a respective one of said circuit portions for receiving an input or output signal for said respective circuit portion during operation of said circuit portion; protective circuits being formed on said semiconductor substrate and each being assigned to a respective one of said circuit portions for preventing overvoltage, said protective circuits each having an input side being connected to a respective one of said connection points and an output side being connected to said respective circuit portion; and a common potential bus bar carrying a reference potential being common with respect to all of said connection points during operation; said protective circuits having discharge paths being coupled with said common potential bus bar for dissipating overvoltages.
Claim 3
Dependent Claim
43 words
The integrated semiconductor circuit according to claim 1, wherein said common potential bus bar is a common potential bar being formed on said semiconductor substrate and carrying a potential being common for all of said circuit portions during operation of the semiconductor circuit.
Claim 4
Dependent Claim
26 words
The integrated semiconductor circuit according to claim 1, wherein said common potential bus bar is a potential ring for a substrate voltage of the semiconductor circuit.
Claim 5
Dependent Claim
40 words
The integrated semiconductor circuit according to claim 1, including at least one pair of diode devices connecting said common potential bus bar to a respective one of said first potential buses and a respective one of said second potential buses.
Claim 6
Dependent Claim
49 words
The integrated semiconductor circuit according to claim 1, including lines each being coupled with a respective one of said connection points, said protective circuits each having a field oxide transistor being formed in said semiconductor substrate and having a gate terminal connected to a respective one of said lines.
Claim 7
Dependent Claim
58 words
The integrated semiconductor circuit according to claim 5, including field-controlled diodes each being connected downstream of a respective one of said field oxide transistors formed in said semiconductor substrate, said field-controlled diodes each having one terminal connected to a respective one of said lines and the another terminal connected to a respective one of said first potential buses.
Claim 8
Dependent Claim
16 words
The integrated semiconductor circuit according to claim 6, wherein said field-controlled diodes are zero volt transistors.
Claim 9
Dependent Claim
51 words
The integrated semiconductor circuit according to claim 6, wherein said field oxide transistors each have another terminal connected to said line, and including diffusion resistors each being connected to said line between a respective one of said field-controlled diodes and said terminals of a respective one of said field oxide transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-12 | 2002-04-13 | 2002-10-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-12 | 2006-04-13 | 2006-10-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-12 | 2010-04-13 | 2010-10-13 | $7700.00 | Window Closed / Lapsed |