US5426323A
Expired / Lapsed
US
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Integrated semiconductor circuit with ESD protection
Assignee: Qimonda AG
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Filing: 1994-05-04
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Granted: 1995-06-20
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Expires: 2014-05-04
Abstract
Abstract An integrated semiconductor circuit includes a semiconductor substrate. At least one first and at least one second potential rail respectively carry first and second supply potentials of the semiconductor circuit during operation. At least one input signal line has at least one input signal terminal and at least one output signal line has at least one output signal terminal and at least one additional line connected to the output signal terminal. At least one first circuit portion receives and processes input signals and at least one second circuit portion develops at least one output signal of the semiconductor circuit during operation of the semiconductor circuit. A configuration for protection against overvoltages has a first protection circuit for each input signal terminal being connected between a respective input signal terminal and a respective first circuit portion, and has a second protection circuit for each output signal terminal being connected to the additional line. Each protection circuit has a field oxide transistor, a field-controlled diode and a diffusion resistor. The potential rails each have a region adjacent at least one of the protection circuits. At least one of the potential rails has a tub-shaped protection structure disposed under the region. The protection structure is disposed in the substrate and is electrically conductively connected to a respective one of the potential rails.
Inventors
- 👤 Werner Reczek
- 👤 Hartmud Terletzki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:59
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/611
Claims Analysis
Total Claims: 48
Claim 1
Independent Claim
480 words
An integrated semiconductor circuit, comprising: a semiconductor substrate; at least one first potential rail carrying a first supply potential of the semiconductor circuit during operation; at least one second potential rail carrying a second supply potential of the semiconductor circuit during operation; at least one input signal line having at least one input signal terminal; at least one output signal line having at least one output signal terminal and at least one additional line connected to said output signal terminal; at least one first circuit portion for receiving and processing input signals; at least one second circuit portion developing at least one output signal of the semiconductor circuit during operation of the semiconductor circuit; a configuration for protection against overvoltages having a first protection circuit for each input signal terminal being connected between a respective input signal terminal and a respective first circuit portion, and having a second protection circuit for each output signal terminal being connected to said additional line; said first protection circuit having: a field oxide transistor and a field-controlled diode disposed electrically parallel with one another between said input signal line and said first potential rail, said field oxide transistor having a gate being connected to said input signal line, said diode having a field control being effected through said first potential rail, and said field oxide transistor and said field-controlled diode being electrically connected to said input signal line at various points along said input signal line; a diffusion resistor in said input signal line between two of said points; said field oxide transistor having a source region, a drain region and respective tub-like regions being formed beneath said source and drain regions, being mutually spaced apart and both being of the same conduction type as said source and drain regions; said second protection circuit having: a field oxide transistor and a field-controlled diode disposed electrically parallel with one another between said additional line and said first potential rail, said field oxide transistor having a gate being connected to said additional line, said diode having a field control being effected through said first potential rail, and said field oxide transistor and said field-controlled diode being electrically connected to said additional line at various points along said additional line; a diffusion resistor in said additional line between two of said points; said field oxide transistor having a source region, a drain region and respective tub-like regions being formed beneath said source and drain regions, being mutually spaced apart and both being of the same conduction type as said source and drain regions; and said potential rails each having a region adjacent at least one of said protection circuits, and at least one of said potential rails having a tub-shaped protection structure disposed under said region, said protection structure being disposed in said substrate and being electrically conductively connected to a respective one of said potential rails.
Claim 2
Dependent Claim
480 words
An integrated semiconductor circuit, comprising: a semiconductor substrate; at least one first potential rail carrying a first supply potential of the semiconductor circuit during operation; at least one second potential rail carrying a second supply potential of the semiconductor circuit during operation; at least one input signal line having at least one input signal terminal; at least one output signal line having at least one output signal terminal and at least one additional line connected to said output signal terminal; at least one first circuit portion for receiving and processing input signals; at least one second circuit portion developing at least one output signal of the semiconductor circuit during operation of the semiconductor circuit; a configuration for protection against overvoltages having a first protection circuit for each input signal terminal being connected between a respective input signal terminal and a respective first circuit portion, and having a second protection circuit for each output signal terminal being connected to said additional line; said first protection circuit having: a field oxide transistor and a field-controlled diode disposed electrically parallel with one another between said input signal line and said first potential rail, said field oxide transistor having a gate being connected to said input signal line, said diode having a field control being effected through said first potential rail, and said field oxide transistor and said field-controlled diode being electrically connected to said input signal line at various points along said input signal line; a diffusion resistor in said input signal line between two of said points; said field oxide transistor having a source region, a drain region and respective tub-like regions being formed beneath said source and drain regions, being mutually spaced apart and both being of the same conduction type as said source and drain regions; said second protection circuit having: a field oxide transistor and a field-controlled diode disposed electrically parallel with one another between said additional line and said first potential rail, said field oxide transistor having a gate being connected to said additional line, said diode having a field control being effected through said first potential rail, and said field oxide transistor and said field-controlled diode being electrically connected to said additional line at various points along said additional line; a diffusion resistor in said additional line between two of said points; said field oxide transistor having a source region, a drain region and respective tub-like regions being formed beneath said source and drain regions, being mutually spaced apart and both being of the same conduction type as said source and drain regions; and said potential rails each having a region adjacent at least one of said protection circuits, and at least one of said potential rails having a tub-shaped protection structure disposed under said region, said protection structure being disposed in said substrate and being electrically conductively connected to a respective one of said potential rails.
Claim 3
Dependent Claim
35 words
The integrated semiconductor circuit according to claim 1, including a region being disposed between said protection structure and a corresponding one of said potential rails, having an increased doping as compared with said protection structure.
Claim 4
Dependent Claim
26 words
The integrated semiconductor circuit according to claim 1, wherein at least one of said protection structures extends as far as a respective one of said terminals.
Claim 5
Dependent Claim
18 words
The integrated semiconductor circuit according to claim 1, wherein said protection structures are at least 5 μm wide.
Claim 6
Dependent Claim
31 words
The integrated semiconductor circuit according to claim 1, wherein said protection structure has a width being at least 10% of a width of said potential rail disposed above said protection structure.
Claim 7
Dependent Claim
29 words
The integrated semiconductor circuit according to claim 1, wherein at least One of said protection structures has a conduction type being opposite a condition type of said semiconductor substrate.
Claim 8
Dependent Claim
31 words
The integrated semiconductor circuit according to claim 1, wherein at least one of said protection structures has a conduction type being the same as a conduction type of said semiconductor substrate.
Claim 9
Dependent Claim
19 words
The integrated semiconductor circuit according to claim 1, including an epitaxial layer on which said semiconductor substrate is disposed.
Claim 10
Dependent Claim
27 words
The integrated semiconductor circuit according to claim 1, wherein said at least one additional line has a lower impedance than said at least one output signal line.
Claim 11
Dependent Claim
24 words
The integrated semiconductor circuit according to claim 9, wherein said at least one output signal line has a resistance of at least two ohms.
Claim 12
Dependent Claim
35 words
The integrated semiconductor circuit according to claim 9, wherein said at least one output signal line has a resistance being distributed uniformly over a region between one of said terminals and said second circuit portion.
Claim 13
Dependent Claim
78 words
The integrated semiconductor circuit according to claim 1, further comprising additional tub-like regions outside said protection configuration of said semiconductor circuit, said additional tub-like regions having different potentials and being of the same conduction type as said tub-like regions of said field oxide transistor, and wherein said tub-like regions beneath said field oxide transistor of a respective one of said protection circuits have a mutual spacing being at most equal to a spacing between said additional tub-like regions.
Claim 14
Dependent Claim
36 words
The integrated semiconductor circuit according to claim 1, including a multiplicity of contacts electrically connecting said source and drain regions of said field oxide transistor of said first protection circuit with said respective underlying tub-like regions.
Claim 15
Dependent Claim
41 words
The integrated semiconductor circuit according to claim 13, wherein said tub-like regions of said first protection circuit additionally have a region of higher doping through which electrical contacting with said source and drain regions of said field .oxide transistor takes place.
Claim 16
Dependent Claim
36 words
The integrated semiconductor circuit according to claim 1, including a multiplicity of contacts electrically connecting said source and drain regions of said field oxide transistor of said second protection circuit with said respective underlying tub-like regions.
Claim 17
Dependent Claim
41 words
The integrated semiconductor circuit according to claim 15, wherein said tub-like regions of said second protection circuit additional have a region of higher doping through which electrical contacting with said source and drain regions of said field oxide transistor takes place.
Claim 18
Dependent Claim
22 words
The integrated semiconductor circuit according to claim 1, wherein said field oxide transistor of said first protection circuit is a finger transistor.
Claim 19
Dependent Claim
22 words
The integrated semiconductor circuit according to claim 1, wherein said field oxide transistor of said second protection circuit is a finger transistor.
Claim 20
Dependent Claim
25 words
The integrated semiconductor circuit according to claim 17, wherein said finger transistor has corners with finger tips, and at least said finger tips are chamfered.
Claim 21
Dependent Claim
25 words
The integrated semiconductor circuit according to claim 18, wherein said finger transistor has corners with finger tips, and at least said finger tips are chamfered.
Claim 22
Dependent Claim
17 words
The integrated semiconductor circuit according to claim 1, wherein said diffusion resistors have a large surface area.
Claim 23
Dependent Claim
26 words
The integrated semiconductor circuit according to claim 1, wherein said protection circuits are each disposed in the immediate vicinity of a respective one of said terminals.
Claim 24
Dependent Claim
16 words
The integrated semiconductor circuit according to claim 1, wherein said field-controlled diodes are zero voltage transistors.
Claim 25
Dependent Claim
23 words
The integrated semiconductor circuit according to claim 23, wherein said zero voltage transistors have gates each being in the shape of a barbell.
Claim 26
Dependent Claim
77 words
The integrated semiconductor circuit according to claim 23, further comprising additional transistors contained outside said protection configuration in the semiconductor circuit, said additional transistors each having a gate with a spacing from a respective source and from a respective drain thereof, and wherein said zero voltage transistors each have a gate with a spacing from a respective source and from a respective drain that amounts to at least 1.5 times a corresponding spacing in said additional transistors.
Claim 27
Dependent Claim
22 words
The integrated semiconductor circuit according to claim 1, including at least one pass gate transistor connected downstream of said first protection circuit.
Claim 28
Dependent Claim
21 words
The integrated semiconductor circuit according to claim 26, wherein said pass gate transistor has a gate receiving the second supply potential.
Claim 29
Dependent Claim
21 words
The integrated semiconductor circuit according to claim 26, wherein said pass gate transistor has a gate through which it is switched.
Claim 30
Dependent Claim
80 words
The integrated semiconductor circuit according to claim 26, further comprising additional transistors contained outside said protection configuration in the semiconductor circuit, said additional transistors each having a gate with a spacing from a respective source and from a respective drain thereof, and wherein said pass gate transistor has a source, a drain and a gate being spaced from said source and said drain by a spacing that amounts to at least 1.5 times a corresponding spacing in said additional transistors.
Claim 31
Dependent Claim
35 words
The integrated semiconductor circuit according to claim 1, including a molybdenum silicide layer connecting said source region of said field oxide transistor of at least one of said protection circuits to said first potential rail.
Claim 32
Dependent Claim
74 words
The integrated semiconductor circuit according to claim 1, including a resistor connecting said source region of said field oxide transistor of at least one of said protection circuits to said first potential rail, said resistor having a resistance being at least five times a resistance that would result if said source region of said field oxide transistor of said at least one protection circuit were connected to said first potential rail without said resistor.
Claim 33
Dependent Claim
35 words
The integrated semiconductor circuit according to claim 1, including a molybdenum silicide layer connecting said drain region of said field oxide transistor of at least one of said protection circuits to one of said lines.
Claim 34
Dependent Claim
73 words
The integrated semiconductor circuit according to claim 1, including a resistor connecting said drain region of said field oxide transistor of at least one of said protection circuits to one of said lines, said resistor having a resistance being at least five times a resistance that would result if said drain region of said field oxide transistor of said at least one protection circuit were connected to said one line without said resistor.
Claim 35
Dependent Claim
31 words
The integrated semiconductor circuit according to claim 1, including at least one diode being disposed between said first and second potential rails and blocking during normal operation of the semiconductor circuit.
Claim 36
Dependent Claim
30 words
The integrated semiconductor circuit according to claim 34, wherein said at least one diode is more than one diode being disposed at mutual spacings of a maximum of 10 millimeters.
Claim 37
Dependent Claim
16 words
The integrated semiconductor circuit according to claim 35, wherein said diodes are disposed at regular intervals.
Claim 38
Dependent Claim
36 words
The integrated semiconductor circuit according to claim 1, including at least one other field oxide transistor being disposed between said first and second potential rails and having a gate being connected to said second potential rail.
Claim 39
Dependent Claim
36 words
The integrated semiconductor circuit according to claim 37, wherein said at least one other field oxide transistor is a plurality of other field oxide transistors being disposed at mutual spacings of a maximum of 10 millimeters.
Claim 40
Dependent Claim
19 words
The integrated semiconductor circuit according to claim 38, wherein said other field oxide transistors are disposed at regular intervals.
Claim 41
Dependent Claim
33 words
The integrated semiconductor circuit according to claim 1, including at least one pair of two antiparallel-connected diode devices connecting together a plurality of said potential rails carrying the same supply potential during operation.
Claim 42
Dependent Claim
20 words
The integrated semiconductor circuit according to claim 40, wherein one of said diode devices has at least one series-connected diode.
Claim 43
Dependent Claim
31 words
The integrated semiconductor circuit according to claim 40, wherein said pairs of diode devices are connected in a star pattern to one of said potential rails having the lowest ohmic resistance.
Claim 44
Dependent Claim
43 words
The integrated semiconductor circuit according to claim 40, wherein said plurality of potential rails carrying the same supply potential during operation each have their own potential terminal, and said at least one pair of diode devices is connected to said respective potential terminals.
Claim 45
Dependent Claim
44 words
The integrated semiconductor circuit according to claim 43, wherein said pairs of diode devices are connected in a star pattern to that potential terminal of said potential rails having the same potential and being connected to said potential rail with the lowest ohmic resistance.
Claim 46
Dependent Claim
76 words
The integrated semiconductor circuit according to claim 1, including at least one terminal carrying a substrate bias potential during operation of the semiconductor circuit; a field oxide transistor being connected between said at least one terminal and said first potential rail and having a gate being connected to said at least one terminal; and one further tub-like region in said field oxide transistor being disposed at least partially beneath one of said drain and source regions.
Claim 47
Dependent Claim
315 words
An integrated semiconductor circuit, Comprising: a semiconductor substrate; at least one first potential rail carrying a first supply potential of the semiconductor circuit during operation; at least one second potential rail carrying a second supply potential of the semiconductor circuit during operation; at least one input signal line and at least one output signal line having terminals for carrying both an input signal and an output signal during operation; at least one first circuit portion for receiving and processing input signals; at least one second circuit portion developing at least one output signal of the semiconductor circuit during operation of the semiconductor circuit; a configuration for protection against overvoltages having a protection circuit for each terminal being connected between a respective terminal and a respective first circuit portion; said protection circuit having: a field oxide transistor and a field-controlled diode disposed electrically parallel with one another between said input signal line and said first potential rail, said field oxide transistor having a gate being connected to said input signal line, said diode having a field control being effected through said first potential rail, and said field oxide transistor and said field-controlled diode being electrically connected to said input signal line at various points along said input signal line; a diffusion resistor in said input signal line between two of said points; said field oxide transistor having a source region, a drain region and respective tub-like regions being formed beneath said source and drain regions, being mutually spaced apart and both being of the same conduction type as said source and drain regions; and at least one of said potential rails having a region adjacent said protection circuit, and at least one of said potential rails having a tub-shaped protection structure disposed under said region, said protection structure being disposed in said substrate and being electrically conductively connected to a respective one of said potential rails.
Claim 48
Dependent Claim
315 words
An integrated semiconductor circuit, Comprising: a semiconductor substrate; at least one first potential rail carrying a first supply potential of the semiconductor circuit during operation; at least one second potential rail carrying a second supply potential of the semiconductor circuit during operation; at least one input signal line and at least one output signal line having terminals for carrying both an input signal and an output signal during operation; at least one first circuit portion for receiving and processing input signals; at least one second circuit portion developing at least one output signal of the semiconductor circuit during operation of the semiconductor circuit; a configuration for protection against overvoltages having a protection circuit for each terminal being connected between a respective terminal and a respective first circuit portion; said protection circuit having: a field oxide transistor and a field-controlled diode disposed electrically parallel with one another between said input signal line and said first potential rail, said field oxide transistor having a gate being connected to said input signal line, said diode having a field control being effected through said first potential rail, and said field oxide transistor and said field-controlled diode being electrically connected to said input signal line at various points along said input signal line; a diffusion resistor in said input signal line between two of said points; said field oxide transistor having a source region, a drain region and respective tub-like regions being formed beneath said source and drain regions, being mutually spaced apart and both being of the same conduction type as said source and drain regions; and at least one of said potential rails having a region adjacent said protection circuit, and at least one of said potential rails having a tub-shaped protection structure disposed under said region, said protection structure being disposed in said substrate and being electrically conductively connected to a respective one of said potential rails.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-06-19 | 1998-12-19 | 1999-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-06-19 | 2002-12-19 | 2003-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-06-19 | 2006-12-19 | 2007-06-20 | $7700.00 | Window Closed / Lapsed |