Patent US5821584A successfully refreshed from Google Patents.
US5821584A
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Thin film transistors comprising drain offset regions
Assignee: Micron Technology Inc
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Filing: 1997-06-27
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Granted: 1998-10-13
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Expires: 2017-06-27
Abstract
Abstract A method of forming a thin film transistor of a first conductivity type includes, a) providing a thin film transistor layer of semiconductive material; b) first masking the thin film transistor layer to mask a desired drain offset region while leaving a desired channel region exposed; c) with the first masking in place, doping the exposed channel region with a conductivity enhancing impurity of a second type; d) second masking the thin film transistor layer to mask the channel region and the drain offset region and leave desired opposing source/drain regions exposed; and e) with the second masking in place, doping the exposed source/drain regions with a conductivity enhancing impurity of the first type. A thin film transistor includes, ii) a thin film layer of semiconductive material, the thin film layer comprising a source region, a drain region, a drain offset region and a channel region; the source and drain regions being conductively doped with a conductivity enhancing impurity of the first type to a concentration effective to render such source and drain regions electrically conductive; the channel region being doped with a conductivity enhancing impurity of a second type to a first concentration; the drain offset region being doped with a conductivity enhancing impurity of the second type to a second concentration, the second concentration being less than the first concentration; and ii) a gate positioned operatively adjacent the channel region. Alternately, the drain offset region consists essentially of undoped semiconductive material.
Inventors
- 👤 Monte Manning
- 👤 Shubneesh Batra
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:16
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/0316; H10D30/0321; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10D30/6717; H10D30/6729; H10D30/673; H10D30/6733; H10D30/6734; H10D30/674
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
110 words
A thin film transistor of a first conductivity type comprising: a thin film layer of semiconductive material, the thin film layer comprising a source region, a drain region, a drain offset region and a channel region; the source region being in physical contact with the channel region, the source and drain regions being conductively doped with a conductivity enhancing impurity of the first conductivity type to a concentration effective to render such source and drain regions electrically conductive; the drain offset region being doped with a conductivity enhancing impurity of a second conductivity type to a concentration which is not identical to a concentration of dopant within the channel region.
Claim 2
Dependent Claim
110 words
A thin film transistor of a first conductivity type comprising: a thin film layer of semiconductive material, the thin film layer comprising a source region, a drain region, a drain offset region and a channel region; the source region being in physical contact with the channel region, the source and drain regions being conductively doped with a conductivity enhancing impurity of the first conductivity type to a concentration effective to render such source and drain regions electrically conductive; the drain offset region being doped with a conductivity enhancing impurity of a second conductivity type to a concentration which is not identical to a concentration of dopant within the channel region.
Claim 3
Dependent Claim
38 words
The thin film transistor of claim 1 wherein the conductivity type of the channel region is the second type, the second type conductivity enhancing impurity of the channel region and the drain offset region being the same impurity.
Claim 4
Dependent Claim
21 words
The thin film transistor of claim 1 wherein the first conductivity type is p and the second conductivity type is n.
Claim 5
Dependent Claim
21 words
The thin film transistor of claim 1 wherein the first conductivity type is n and the second conductivity type is p.
Claim 6
Dependent Claim
114 words
A thin film transistor of a first conductivity type comprising: a thin film layer of semiconductive material, the thin film layer comprising a source region, a drain region, a drain offset region and a channel region; the source and drain regions being conductively doped with a conductivity enhancing impurity of the first conductivity type to a concentration effective to render such source and drain regions electrically conductive; the drain offset region being doped with a conductivity enhancing impurity of a second conductivity type to a concentration which is not identical to a concentration of dopant within the channel region; a gate positioned operatively adjacent the channel region; and the drain offset not being gated.
Claim 7
Dependent Claim
114 words
A thin film transistor of a first conductivity type comprising: a thin film layer of semiconductive material, the thin film layer comprising a source region, a drain region, a drain offset region and a channel region; the source and drain regions being conductively doped with a conductivity enhancing impurity of the first conductivity type to a concentration effective to render such source and drain regions electrically conductive; the drain offset region being doped with a conductivity enhancing impurity of a second conductivity type to a concentration which is not identical to a concentration of dopant within the channel region; a gate positioned operatively adjacent the channel region; and the drain offset not being gated.
Claim 8
Dependent Claim
77 words
A thin film transistor of a first conductivity type comprising: a thin film layer of semiconductive material, the thin film layer comprising a drain offset region and a channel region; the drain offset region being doped with a conductivity enhancing impurity of a second conductivity type to a concentration which is not identical to a concentration of dopant within the channel region; a gate positioned operatively adjacent the channel region; and the drain offset not being gated.
Claim 9
Dependent Claim
77 words
A thin film transistor of a first conductivity type comprising: a thin film layer of semiconductive material, the thin film layer comprising a drain offset region and a channel region; the drain offset region being doped with a conductivity enhancing impurity of a second conductivity type to a concentration which is not identical to a concentration of dopant within the channel region; a gate positioned operatively adjacent the channel region; and the drain offset not being gated.
Claim 10
Dependent Claim
118 words
A thin film transistor of a first conductivity type comprising: a thin film layer of polysilicon, the thin film layer comprising a source region, a drain region, a drain offset region and a channel region; the source and drain regions being conductively doped with a conductivity enhancing impurity of the first conductivity type to a concentration effective to render such source and drain regions electrically conductive; the channel region being doped with a conductivity enhancing impurity to a first concentration; the drain offset region being doped with a conductivity enhancing impurity of a second conductivity type to a second concentration, the second concentration being less than the first concentration; and a gate positioned operatively adjacent the channel region.
Claim 11
Dependent Claim
118 words
A thin film transistor of a first conductivity type comprising: a thin film layer of polysilicon, the thin film layer comprising a source region, a drain region, a drain offset region and a channel region; the source and drain regions being conductively doped with a conductivity enhancing impurity of the first conductivity type to a concentration effective to render such source and drain regions electrically conductive; the channel region being doped with a conductivity enhancing impurity to a first concentration; the drain offset region being doped with a conductivity enhancing impurity of a second conductivity type to a second concentration, the second concentration being less than the first concentration; and a gate positioned operatively adjacent the channel region.
Claim 12
Dependent Claim
129 words
A thin film transistor of a first conductivity type comprising: a thin film layer of polysilicon, the thin film layer comprising a source region, a drain region, a drain offset region and a channel region the source region being in physical contact with the channel region; the source and drain regions being conductively doped with a conductivity enhancing impurity of the first conductivity type to a concentration effective to render such source and drain regions electrically conductive; the channel region being doped with a conductivity enhancing impurity to a first concentration; the drain offset region being doped with a conductivity enhancing impurity of a second conductivity type to a second concentration, the second concentration being less than the first concentration; and a gate positioned operatively adjacent the channel region.
Claim 13
Dependent Claim
129 words
A thin film transistor of a first conductivity type comprising: a thin film layer of polysilicon, the thin film layer comprising a source region, a drain region, a drain offset region and a channel region the source region being in physical contact with the channel region; the source and drain regions being conductively doped with a conductivity enhancing impurity of the first conductivity type to a concentration effective to render such source and drain regions electrically conductive; the channel region being doped with a conductivity enhancing impurity to a first concentration; the drain offset region being doped with a conductivity enhancing impurity of a second conductivity type to a second concentration, the second concentration being less than the first concentration; and a gate positioned operatively adjacent the channel region.
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