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US5819065A
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System and method for emulating memory
Assignee: Cadence Design Systems Inc
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Filing: 1996-02-06
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Granted: 1998-10-06
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Expires: 2016-02-06
Abstract
Abstract A system and method for emulating memory designs is described. The system includes a time sliced logic emulator. The time sliced logic emulator emulates the functions performed in one cycle of a target design by emulating portions of the functions in a set of time slices. That is, a set of time slices represents a single clock cycle in the target design. The system emulates many different types of memory designs included in the target design. The system includes an emulation memory. The memory designs are mapped to the emulation memory via a programmable address generation block. For a given time slice, the programmable address generation block generates an address that maps all or part of a memory design address to an emulation memory address. The programmable address generation block allows multiple memory designs to be mapped to a single emulation memory and allows a single memory design to be mapped to multiple emulation memories. Thus, over multiple time slices, the system can emulate many different types of memories.
Inventors
- 👤 John E. Chilton
- 👤 Tony R. Sarno
- 👤 Ingo Schaefer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 16:44
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/261; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/331
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
151 words
An emulation memory comprising: a memory circuit having an address port and a data port; an address circuit having an address output port coupled to said address port, said address circuit being programmable, said address circuit mapping a set of addresses of a plurality of target memories to a set of emulation memory addresses over a set of time periods, said set of target memories includes a first target memory of a first type and a second target memory of a second type, said first target memory and said second target memory for receiving addresses during a single cycle of a target design, and wherein said address circuit is for generating a first emulation address corresponding to a first target memory address during a first cycle of said emulation memory, and a second target memory address corresponding to a second target memory address during a second cycle of said emulation memory.
Claim 2
Dependent Claim
151 words
An emulation memory comprising: a memory circuit having an address port and a data port; an address circuit having an address output port coupled to said address port, said address circuit being programmable, said address circuit mapping a set of addresses of a plurality of target memories to a set of emulation memory addresses over a set of time periods, said set of target memories includes a first target memory of a first type and a second target memory of a second type, said first target memory and said second target memory for receiving addresses during a single cycle of a target design, and wherein said address circuit is for generating a first emulation address corresponding to a first target memory address during a first cycle of said emulation memory, and a second target memory address corresponding to a second target memory address during a second cycle of said emulation memory.
Claim 3
Dependent Claim
178 words
An emulation memory comprising: a memory circuit having an address port and a data port: an address circuit having an address output port coupled to said address port, said address circuit being programmable, said address circuit mapping a set of addresses of a plurality of target memories to a set of emulation memory addresses over a set of time periods, said emulation memory further including a first memory circuit and a second memory circuit, each memory circuit for storing an N words of data, and wherein said set of target memories includes a first target memory design for storing a M words of data, where M is greater than N, and wherein said address circuit includes a first address circuit for generating a first set of emulation addresses for said first memory corresponding to N words of data of said M words of data, and wherein said address circuit includes a second address circuit for generating a set of second emulation addresses for said second memory corresponding to M-N words of data of said M words of data.
Claim 4
Dependent Claim
178 words
An emulation memory comprising: a memory circuit having an address port and a data port: an address circuit having an address output port coupled to said address port, said address circuit being programmable, said address circuit mapping a set of addresses of a plurality of target memories to a set of emulation memory addresses over a set of time periods, said emulation memory further including a first memory circuit and a second memory circuit, each memory circuit for storing an N words of data, and wherein said set of target memories includes a first target memory design for storing a M words of data, where M is greater than N, and wherein said address circuit includes a first address circuit for generating a first set of emulation addresses for said first memory corresponding to N words of data of said M words of data, and wherein said address circuit includes a second address circuit for generating a set of second emulation addresses for said second memory corresponding to M-N words of data of said M words of data.
Claim 5
Dependent Claim
49 words
The emulation memory of claim 2 wherein N is 4096 and M is 6144 and said first set of emulation addresses correspond to word zero through word 4095 of said M words of data and where said second set of emulation addresses correspond to word 4096 through word 6143.
Claim 6
Dependent Claim
159 words
An emulation memory comprising: a memory circuit having an address port and a data port; an address circuit having an address output port coupled to said address port, said address circuit being programmable, said address circuit mapping a set of addresses of a plurality of target memories to a set of emulation memory addresses over a set of time periods; a first memory circuit for storing an N bit wide data word, and wherein said set of target memories includes a first target memory design for storing a M bit wide data word, where M is greater than N, and wherein said address circuit includes a first address circuit for generating a first emulation address for said first memory corresponding to N bits of said M bit wide data word, and wherein said first address circuit is for generating a second emulation address for said first memory circuit corresponding to M-N bits of said M bit wide data word.
Claim 7
Dependent Claim
159 words
An emulation memory comprising: a memory circuit having an address port and a data port; an address circuit having an address output port coupled to said address port, said address circuit being programmable, said address circuit mapping a set of addresses of a plurality of target memories to a set of emulation memory addresses over a set of time periods; a first memory circuit for storing an N bit wide data word, and wherein said set of target memories includes a first target memory design for storing a M bit wide data word, where M is greater than N, and wherein said address circuit includes a first address circuit for generating a first emulation address for said first memory corresponding to N bits of said M bit wide data word, and wherein said first address circuit is for generating a second emulation address for said first memory circuit corresponding to M-N bits of said M bit wide data word.
Claim 8
Dependent Claim
14 words
The emulation memory of claim 4 wherein N is thirty-two and M is sixty-four.
Claim 9
Independent Claim
189 words
a method of emulating a set of memory designs in an emulator, said emulator including an address circuit and a memory circuit, said memory circuit includes a set of emulation memories, each emulation memory being N bits in size, and wherein a first memory design being M bits in size, M being greater than N said method comprising: mapping each memory design to an address space in said memory circuit and to a set of time slices, said set of time slices corresponding to a cycle in said each memory design, said mapping step further comprising: mapping N low order bits of said first memory design to a first emulation memory; mapping M-N high order bits of said first memory design to a second emulation memory; responsive to receiving a memory design function command, performing the following, generating a set of memory addresses in said address space over a corresponding set of time slices; and performing a set of memory functions on said memory circuit over said corresponding set of time slices and using said set of memory addresses, said set of memory functions emulation said memory design function.
Claim 10
Independent Claim
189 words
a method of emulating a set of memory designs in an emulator, said emulator including an address circuit and a memory circuit, said memory circuit includes a set of emulation memories, each emulation memory being N bits in size, and wherein a first memory design being M bits in size, M being greater than N said method comprising: mapping each memory design to an address space in said memory circuit and to a set of time slices, said set of time slices corresponding to a cycle in said each memory design, said mapping step further comprising: mapping N low order bits of said first memory design to a first emulation memory; mapping M-N high order bits of said first memory design to a second emulation memory; responsive to receiving a memory design function command, performing the following, generating a set of memory addresses in said address space over a corresponding set of time slices; and performing a set of memory functions on said memory circuit over said corresponding set of time slices and using said set of memory addresses, said set of memory functions emulation said memory design function.
Claim 11
Dependent Claim
10 words
The method of claim 6 wherein N is 131,072 bits.
Claim 12
Independent Claim
193 words
A method of emulating a set of memory designs in an emulator, said emulator including an address circuit and a memory circuit, said memory circuit includes an emulation memory having a 32 bit word and wherein a first memory design having a 64 bit wide word said method comprising: mapping each memory design to an address space in said memory circuit and to a set of time slices, said set of time slices corresponding to a cycle in said each memory design, said mapping step further comprises: mapping bits 31-0 of said 64 bit wide word to a first word of a first pair of words in said emulation memory; and mapping bits 63-32 of said 64 bit wide word to a second word of said first pair of words; responsive to receiving a memory design function command, performing the following, generating a set of memory addresses in said address space over a corresponding set of time slices; and performing a set of memory functions on said memory circuit over said corresponding set of time slices and using said set of memory addresses, said set of memory functions emulating said memory design function.
Claim 13
Independent Claim
193 words
A method of emulating a set of memory designs in an emulator, said emulator including an address circuit and a memory circuit, said memory circuit includes an emulation memory having a 32 bit word and wherein a first memory design having a 64 bit wide word said method comprising: mapping each memory design to an address space in said memory circuit and to a set of time slices, said set of time slices corresponding to a cycle in said each memory design, said mapping step further comprises: mapping bits 31-0 of said 64 bit wide word to a first word of a first pair of words in said emulation memory; and mapping bits 63-32 of said 64 bit wide word to a second word of said first pair of words; responsive to receiving a memory design function command, performing the following, generating a set of memory addresses in said address space over a corresponding set of time slices; and performing a set of memory functions on said memory circuit over said corresponding set of time slices and using said set of memory addresses, said set of memory functions emulating said memory design function.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-05 | 2002-04-06 | 2002-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-05 | 2006-04-06 | 2006-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-05 | 2010-04-06 | 2010-10-06 | $7700.00 | Window Closed / Lapsed |