US5818748A — Chip function separation onto separate stacked ch…

Claim 1

Independent Claim 84 words

A three-dimensional semiconductor chip having a given overall function comprised of a plurality of subfunctions, comprising: a first semiconductor chip comprising circuitry on a first surface thereof for performing a first portion of said plurality of subfunctions; a second semiconductor chip vertically adjacent said first semiconductor chip, said second semiconductor chip comprising circuitry on a second surface thereof for performing a second portion of said plurality of subfunctions; and a plurality of connectors for connecting said first semiconductor chip and said second semiconductor chip.

Claim 2

Dependent Claim 84 words

A three-dimensional semiconductor chip having a given overall function comprised of a plurality of subfunctions, comprising: a first semiconductor chip comprising circuitry on a first surface thereof for performing a first portion of said plurality of subfunctions; a second semiconductor chip vertically adjacent said first semiconductor chip, said second semiconductor chip comprising circuitry on a second surface thereof for performing a second portion of said plurality of subfunctions; and a plurality of connectors for connecting said first semiconductor chip and said second semiconductor chip.

Claim 3

Dependent Claim 25 words

The three-dimensional semiconductor chip of claim 1 wherein said plurality of connectors comprise a plurality of force-responsive self-interlocking microconnectors disposed on each said semiconductor chip.

Claim 4

Dependent Claim 32 words

The three-dimensional semiconductor chip of claim 2 wherein said plurality of force-responsive self-interlocking microconnectors provide both a physical and an electrical connection between said first semiconductor chip and said second semiconductor chip.

Claim 5

Dependent Claim 32 words

The three-dimensional semiconductor chip of claim 2, wherein said plurality of force-responsive self-interlocking microconnectors provide a physical connection, and wherein said plurality of connectors also comprise a plurality of reflowable electrical connections.

Claim 6

Dependent Claim 33 words

The three-dimensional semiconductor chip of claim 2 wherein said plurality of force-responsive self-interlocking microconnectors are located in at least two channels oppositely disposed on said first semiconductor chip and said second semiconductor chip.

Claim 7

Dependent Claim 17 words

The three-dimensional semiconductor chip of claim 5 wherein said at least two channels comprise a raised area.

Claim 8

Dependent Claim 16 words

The three-dimensional semiconductor chip of claim 5 wherein said at least two channels comprise an inset.

Claim 9

Dependent Claim 20 words

The three-dimensional semiconductor chip of claim 5 wherein said at least two channels comprise a raised area and an inset.

Claim 10

Dependent Claim 68 words

The three-dimensional semiconductor chip of claim 2, wherein said plurality of connectors further comprise a plurality of repelling members disposed on one of said first semiconductor chip and said second semiconductor chip, said plurality of repelling members tending to push away a semiconductor chip coming into contact therewith, and said plurality of force-responsive self-interlocking microconnectors tending to pull said first semiconductor chip and said second semiconductor chip together.

Claim 11

Dependent Claim 23 words

The three-dimensional semiconductor chip of claim 2, wherein said plurality of force-responsive self-interlocking microconnectors comprise a plurality of sizes providing differing alignment accuracy.

Claim 12

Dependent Claim 36 words

The three-dimensional semiconductor chip of claim 2 wherein said plurality of force-responsive self-interlocking microconnectors are located in a continuous channel around an outer portion of each of said first semiconductor chip and said second semiconductor chip.

Claim 13

Dependent Claim 56 words

The three-dimensional semiconductor chip of claim 1, wherein said plurality of connectors comprise a plurality of metal bumps oppositely disposed on a facing surface of each said semiconductor chip, said three-dimensional semiconductor chip further comprising a means for connecting corresponding said oppositely disposed plurality of metal bumps, thereby providing both a physical and an electrical connection.

Claim 14

Dependent Claim 66 words

The three-dimensional semiconductor chip of claim 1, wherein said given overall function is that of a memory array, wherein said circuitry of said first semiconductor chip comprises a plurality of array lines, wherein said second semiconductor chip comprises a plurality of drivers for said plurality of array lines and wherein said plurality of connectors electrically couple said plurality of array lines and said plurality of drivers.

Claim 15

Dependent Claim 19 words

The three-dimensional semiconductor chip of claim 13 wherein said plurality of array lines comprise a plurality of word lines.

Claim 16

Dependent Claim 19 words

The three-dimensional semiconductor chip of claim 13 wherein said plurality of drivers comprise a plurality of high voltage drivers.

Claim 17

Dependent Claim 82 words

A three-dimensional direct-write EEPROM memory array, comprising: a first semiconductor chip comprising a plurality of array lines on a first surface thereof, said plurality of array lines including a plurality of direct-write EEPROM devices; a second semiconductor chip vertically adjacent said first semiconductor chip, said second semiconductor chip comprising a plurality of drivers on a second surface thereof corresponding to said plurality of direct-write EEPROM devices; and a plurality of connectors for connecting said first semiconductor chip and said second semiconductor chip.

Claim 18

Dependent Claim 82 words

A three-dimensional direct-write EEPROM memory array, comprising: a first semiconductor chip comprising a plurality of array lines on a first surface thereof, said plurality of array lines including a plurality of direct-write EEPROM devices; a second semiconductor chip vertically adjacent said first semiconductor chip, said second semiconductor chip comprising a plurality of drivers on a second surface thereof corresponding to said plurality of direct-write EEPROM devices; and a plurality of connectors for connecting said first semiconductor chip and said second semiconductor chip.

Claim 19

Dependent Claim 27 words

The three-dimensional direct-write EEPROM memory array of claim 16 wherein said plurality of drivers comprise a driver capable of generating a voltage of more than 5 volts.

Claim 20

Dependent Claim 31 words

The three-dimensional direct-write EEPROM memory array of claim 17 wherein said driver capable of generating more than 5 volts is capable of generating a voltage of at least about 10 volts.

Claim 21

Dependent Claim 26 words

The three-dimensional direct-write EEPROM memory array of claim 16, wherein said second semiconductor chip further comprises a plurality of decoders for said plurality of array lines.

Claim 22

Dependent Claim 32 words

The three-dimensional direct-write EEPROM memory array of claim 16 wherein said plurality of connectors comprise a plurality of force-responsive self-interlocking microconnectors disposed on each of said first surface and said second surface.

Claim 23

Dependent Claim 46 words

The three-dimensional direct-write EEPROM memory array of claim 16, wherein said plurality of electrical connectors comprise a plurality of metal bumps oppositely disposed on each of said first surface and said second surface and wherein an adhesive connects corresponding said oppositely disposed plurality of metal bumps.

Claim 24

Independent Claim 57 words

A method for decreasing semiconductor chip area for a semiconductor chip having a given overall function comprised of a plurality of subfunctions, said method comprising steps of: separating circuitry corresponding to said plurality of subfunctions onto at least two vertically adjacent semiconductor chips; and connecting said at least two semiconductor chips, thereby forming a three-dimensional semiconductor chip.

Claim 25

Independent Claim 57 words

A method for decreasing semiconductor chip area for a semiconductor chip having a given overall function comprised of a plurality of subfunctions, said method comprising steps of: separating circuitry corresponding to said plurality of subfunctions onto at least two vertically adjacent semiconductor chips; and connecting said at least two semiconductor chips, thereby forming a three-dimensional semiconductor chip.

Claim 26

Dependent Claim 49 words

The method of claim 22 wherein said step of connecting comprises: forming a plurality of metal bumps oppositely disposed on joining surfaces of said at least two vertically adjacent semiconductor chips; and connecting said oppositely disposed plurality of metal bumps, thereby providing both a physical and an electrical connection.

Claim 27

Dependent Claim 32 words

The method of claim 22, wherein said step of connecting comprises forming a plurality of force-responsive self-interlocking microconnectors oppositely disposed on joining surfaces of said at least two vertically adjacent semiconductor chips.

Claim 28

Dependent Claim 38 words

The method of claim 24, wherein said step of connecting further comprises forming a plurality of reflowable electrical connections between said at least two vertically adjacent semiconductor chips, said plurality of force-responsive self-interlocking microconnectors providing a physical connection.

Claim 29

Dependent Claim 24 words

The method of claim 24, wherein said step of forming comprises creating a channel on which to form said plurality of force-responsive self-interlocking microconnectors.

Claim 30

Dependent Claim 25 words

The method of claim 26, wherein said step of creating comprises creating a raised area on which to form said plurality of force-responsive self-interlocking microconnectors.

Claim 31

Dependent Claim 25 words

The method of claim 26, wherein said step of creating comprises creating a recessed area in which to form said plurality of force-responsive self-interlocking microconnectors.

Claim 32

Dependent Claim 44 words

The method of claim 24, wherein said step of connecting further comprises forming a plurality of micromembers tending to push away a vertically adjacent semiconductor chip, said plurality of force-responsive self-interlocking microconnectors tending to pull said at least two vertically adjacent semiconductor chips together.

Claim 33

Dependent Claim 26 words

The method of claim 24, wherein said step of forming comprises forming a plurality of different sized force-responsive self-interlocking microconnectors providing varying degrees of alignment accuracy.

Claim 34

Dependent Claim 95 words

The method of claim 22, wherein said given overall function is that of a memory array, said memory array including a plurality of array lines and a plurality of drivers corresponding to said plurality of array lines, wherein said step of separating comprises placing said plurality of array lines on one of said at least two vertically adjacent semiconductor chips and said plurality of drivers on another of said at least two vertically adjacent semiconductor chips, and wherein said step of connecting comprises electrically connecting said plurality of array lines and said plurality of drivers.

Claim 35

Dependent Claim 61 words

The method of claim 31, wherein said plurality of array lines comprise a plurality of word lines, wherein said step of separating comprises placing said plurality of word lines on said one of said at least two vertically adjacent semiconductor chips, and wherein said step of electrically connecting comprises electrically connecting said plurality of word lines with said plurality of drivers.

Claim 36

Dependent Claim 74 words

The method of claim 32, wherein said memory array comprises a direct-write EEPROM memory array, wherein said plurality of drivers comprise a plurality of high voltage drivers, wherein said step of separating comprises placing said plurality of high voltage drivers on said another of said at least two vertically adjacent semiconductor chips, and wherein said step of electrically connecting comprises electrically connecting said plurality of word lines with said plurality of high voltage drivers.

Claim 37

Dependent Claim 33 words

The method of claim 24 wherein said step of forming comprises forming said plurality of force-responsive self-interlocking microconnectors on a joining surface of each of said at least two vertically adjacent semiconductor chips.

Claim 38

Dependent Claim 15 words

The three-dimensional semiconductor chip of claim 1, wherein said first surface faces said second surface.

Claim 39

Dependent Claim 19 words

The three-dimensional semiconductor chip of claim 1, wherein said plurality of connectors comprises a plurality of reflowable electrical connections.

Claim 40

Dependent Claim 16 words

The three-dimensional semiconductor chip of claim 36, wherein said plurality of reflowable electrical connections comprises solder.

Claim 41

Dependent Claim 16 words

The three-dimensional semiconductor chip of claim 1, wherein said first semiconductor chip comprises a memory array.

Claim 42

Dependent Claim 40 words

The three-dimensional semiconductor chip of claim 1, wherein connection of said first semiconductor chip and said second semiconductor chip is essential to enable said first portion of said plurality of subfunctions and said second portion of said plurality of subfunctions.

Claim 43

Dependent Claim 36 words

The three-dimensional semiconductor chip of claim 1, wherein said first semiconductor chip comprises a programmable element for modifying said circuitry on said second semiconductor chip after connecting said first semiconductor chip and said second semiconductor chip.

Claim 44

Dependent Claim 125 words

A three-dimensional semiconductor structure having a given overall function comprised of a plurality of subfunctions, comprising: a first semiconductor chip comprising circuitry on a first surface thereof for performing a first subfunction of said plurality of subfunctions; a second semiconductor chip vertically adjacent said first semiconductor chip, said second semiconductor chip comprising circuitry on a second surface thereof for performing a second subfunction of said plurality of subfunctions different from said first subfunction, said second surface facing said first surface; and a plurality of connectors for connecting said circuitry on said first semiconductor chip and said circuitry on said second semiconductor chip, wherein connection of said first semiconductor chip and said second semiconductor chip is essential to enable said first subfunction and said second subfunction.

Claim 45

Dependent Claim 125 words

A three-dimensional semiconductor structure having a given overall function comprised of a plurality of subfunctions, comprising: a first semiconductor chip comprising circuitry on a first surface thereof for performing a first subfunction of said plurality of subfunctions; a second semiconductor chip vertically adjacent said first semiconductor chip, said second semiconductor chip comprising circuitry on a second surface thereof for performing a second subfunction of said plurality of subfunctions different from said first subfunction, said second surface facing said first surface; and a plurality of connectors for connecting said circuitry on said first semiconductor chip and said circuitry on said second semiconductor chip, wherein connection of said first semiconductor chip and said second semiconductor chip is essential to enable said first subfunction and said second subfunction.

Claim 46

Dependent Claim 25 words

The three-dimensional semiconductor chip of claim 41, wherein said plurality of connectors comprise a plurality of force-responsive self-interlocking microconnectors disposed on each said semiconductor chip.

Claim 47

Dependent Claim 32 words

The three-dimensional semiconductor chip of claim 42, wherein said plurality of force-responsive self-interlocking microconnectors provide both a physical and an electrical connection between said first semiconductor chip and said second semiconductor chip.

Claim 48

Dependent Claim 68 words

The three-dimensional semiconductor chip of claim 42, wherein said plurality of connectors further comprise a plurality of repelling members disposed on one of said first semiconductor chip and said second semiconductor chip, said plurality of repelling members tending to push away a semiconductor chip coming into contact therewith, and said plurality of force-responsive self-interlocking microconnectors tending to pull said first semiconductor chip and said second semiconductor chip together.

Claim 49

Dependent Claim 23 words

The three-dimensional semiconductor chip of claim 42, wherein said plurality of force-responsive self-interlocking microconnectors comprise a plurality of sizes providing differing alignment accuracy.

Claim 50

Dependent Claim 19 words

The three-dimensional semiconductor chip of claim 41, wherein said plurality of connectors comprises a plurality of reflowable electrical connections.

Claim 51

Dependent Claim 16 words

The three-dimensional semiconductor chip of claim 46, wherein said plurality of reflowable electrical connections comprises solder.

Claim 52

Dependent Claim 16 words

The three-dimensional semiconductor chip of claim 41, wherein said first semiconductor chip comprises a memory array.

Claim 53

Dependent Claim 36 words

The three-dimensional semiconductor chip of claim 41, wherein said first semiconductor chip comprises a programmable element for modifying said circuitry on said second semiconductor chip after connecting said first semiconductor chip and said second semiconductor chip.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2001-10-05	2002-04-06	2002-10-06	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2005-10-05	2006-04-06	2006-10-06	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2009-10-05	2010-04-06	2010-10-06	$7700.00	Window Closed / Lapsed

Chip function separation onto separate stacked chips

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