Patent US5818728A successfully refreshed from Google Patents.
US5818728A
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Mapping of gate arrays
Assignee: Chip Express Israel Ltd
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Filing: 1996-03-15
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Granted: 1998-10-06
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Expires: 2016-03-15
Abstract
Abstract This invention discloses a gate array device, useful either as a configurable gate array device or a compact gate array device, comprising an array of two-gate logic cells arranged in columns, a metal grid interconnecting said logic cells into clusters of macrocells, said grid comprising a bottom metal layer and at least one metal layer disposed over the bottom metal layer, power and ground lines formed of said bottom metal layer, extending generally parallel to said columns and a routing grid interconnecting said clusters of macrocells, said routing grid comprising parallel metal tracks crossing said columns of logic cells, and wherein no more than two of said parallel metal tracks are employed to connect to each logic cell.
Inventors
- 👤 Uzi Yoeli
- 👤 Meir Janai
- 👤 Zvi Orbach
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 04:00
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907; H10D89/00; H10D89/10
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
80 words
A method of producing a high density gate array including: providing a programmable gate array; programming the gate array; following programming of the gate array, modifying a computer file of the gate array as programmed, thereby to produce a modified computer file of a programmed gate array wherein at least one metal layer of the gate array is reconfigured so as to increase the density thereof; and employing the modified computer file to mass produce high density programmed gate arrays.
Claim 2
Independent Claim
80 words
A method of producing a high density gate array including: providing a programmable gate array; programming the gate array; following programming of the gate array, modifying a computer file of the gate array as programmed, thereby to produce a modified computer file of a programmed gate array wherein at least one metal layer of the gate array is reconfigured so as to increase the density thereof; and employing the modified computer file to mass produce high density programmed gate arrays.
Claim 3
Dependent Claim
18 words
A method according to claim 1 and wherein said programming of the gate array is done by laser.
Claim 4
Dependent Claim
18 words
A method according to claim 1 and wherein said programming of the gate array is done by photolithography.
Claim 5
Independent Claim
94 words
A method of mapping a relatively less compact gate array device into a relatively more compact gate array device including: providing a relatively less compact gate array having a plurality of logic cells arranged along a given axis and a metal interconnect grid including a plurality of metal layers interconnected by vias at via sites, wherein each logic cell has a length spanning n via sites; mapping said relatively less compact gate array onto a relatively more compact gate array wherein each logic cell has a length spanning no more than n-1/2 via sites.
Claim 6
Independent Claim
94 words
A method of mapping a relatively less compact gate array device into a relatively more compact gate array device including: providing a relatively less compact gate array having a plurality of logic cells arranged along a given axis and a metal interconnect grid including a plurality of metal layers interconnected by vias at via sites, wherein each logic cell has a length spanning n via sites; mapping said relatively less compact gate array onto a relatively more compact gate array wherein each logic cell has a length spanning no more than n-1/2 via sites.
Claim 7
Dependent Claim
23 words
A method according to claim 4 and wherein n is greater than or equal to 3 and less than or equal to 4.
Claim 8
Dependent Claim
51 words
A method according to claim 4 and wherein each of the logic cells in the relatively more compact gate array comprises a plurality of transistors whose width is reduced as compared with the width of a plurality of transistors employed in the logic cells of the relatively less compact gate array.
Claim 9
Independent Claim
154 words
A method of mapping a relatively less compact gate array device having a first plurality of gates into a relatively more compact gate array device having a second plurality of gates, less than the first plurality, the method including: providing a relatively less compact gate array having a first plurality of gates and covering a first rectangular area; utilizing a third plurality of gates in the relatively less compact gate array, said third plurality being less than or equal to said second plurality and being arranged within a rectangular block of area less than the first rectangular area; and mapping the third plurality of gates to a more compact gate array device having an area less than the area of said rectangular block and comprising said second plurality of gates, wherein the number of gates of said second plurality of gates is not less than the number of gates contained in said rectangular block.
Claim 10
Independent Claim
154 words
A method of mapping a relatively less compact gate array device having a first plurality of gates into a relatively more compact gate array device having a second plurality of gates, less than the first plurality, the method including: providing a relatively less compact gate array having a first plurality of gates and covering a first rectangular area; utilizing a third plurality of gates in the relatively less compact gate array, said third plurality being less than or equal to said second plurality and being arranged within a rectangular block of area less than the first rectangular area; and mapping the third plurality of gates to a more compact gate array device having an area less than the area of said rectangular block and comprising said second plurality of gates, wherein the number of gates of said second plurality of gates is not less than the number of gates contained in said rectangular block.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-05 | 2002-04-06 | 2002-10-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-05 | 2006-04-06 | 2006-10-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-05 | 2010-04-06 | 2010-10-06 | $7700.00 | Window Closed / Lapsed |