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US5811338A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of making an asymmetric transistor

Assignee: Micron Technology Inc
•
Filing: 1996-08-09
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Granted: 1998-09-22
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Expires: 2016-08-09
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Abstract

Abstract In one aspect, a method for forming a transistor device on a semiconductor substrate, comprising: a) forming a transistor gate on the. substrate; b) forming a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; and c) forming a second polarity internal junction region, the second polarity internal junction region being entirely received within one of the first polarity regions. In another aspect, a transistor device, comprising: a) a transistor gate on a semiconductor substrate; b) a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; and c) a second polarity internal junction region entirely received within one of the first polarity regions. In yet another aspect, A resistor, comprising: a) a gate on a semiconductor substrate, the gate being electrically powered with a gate voltage; b) a first polarity source active region and a first polarity drain active region operatively adjacent the electrically powered gate; c) a second polarity internal junction region entirely received within one of the first polarity regions; and d) a current between the first polarity source active region and the first polarity drain active region, the current being substantially linearly dependent on a voltage at the drain region.

Inventors

  • 👤 David Y. Kao
  • 👤 Jeff Zhiqiang Wu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 21:44
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/0221; H10D30/60; H10D30/601; H10D30/603; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10D62/235; H10D62/299; H10D62/307

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 133 words
A method for forming a transistor device on a semiconductor substrate comprising the following steps: forming a transistor gate on the semiconductor substrate, the transistor gate comprising lateral edges; defining a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; forming first polarity LDD regions within the source and drain active regions; forming first polarity source and drain regions within the source and drain active regions; forming a second polarity internal junction region, the second polarity internal junction region being entirely received within one or more of the first polarity regions; and before forming the second polarity internal junction region, forming a masking layer over the source active region, the masking layer preventing said internal junction region from being formed within the source active region.
Claim 2
Independent Claim 133 words
A method for forming a transistor device on a semiconductor substrate comprising the following steps: forming a transistor gate on the semiconductor substrate, the transistor gate comprising lateral edges; defining a first polarity source active region and a first polarity drain active region operatively adjacent the transistor gate; forming first polarity LDD regions within the source and drain active regions; forming first polarity source and drain regions within the source and drain active regions; forming a second polarity internal junction region, the second polarity internal junction region being entirely received within one or more of the first polarity regions; and before forming the second polarity internal junction region, forming a masking layer over the source active region, the masking layer preventing said internal junction region from being formed within the source active region.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-09-21 2002-03-23 2002-09-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-09-21 2006-03-23 2006-09-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-09-21 2010-03-23 2010-09-22 $7700.00 Window Closed / Lapsed

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