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US5809322A
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Apparatus and method for signal processing
Assignee: Asp Solutions Ltd
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Filing: 1994-12-09
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Granted: 1998-09-15
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Expires: 2014-12-09
Abstract
Abstract Associative signal processing apparatus for processing an incoming signal including a plurality of samples, the apparatus including a two-dimensional array of processors, each processor including a multiplicity of content addressable memory cells, each sample of an incoming signal being processed by at least one of the processors, and a register array including at least one register operative to store responders arriving from the processors and to provide communication, within a single cycle, between non-adjacent processors.
Inventors
- 👤 Avidan Akerib
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 21:33
CPC Classifications
G; G06; G06T; G06T7/00; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8007; G06F15/8023; G06F15/8038; G06V; G06V10/00; G06V10/40; G06V10/44; G06V10/443; G06V10/94; G06V10/955
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
100 words
Associative signal processing apparatus for processing an incoming signal comprising a plurality of samples, the apparatus comprising: an array of processors, each processor including a multiplicity of content addressable memory (CAM) cells, said array forming a two dimensional array of said content addressable memory cells, each sample of an incoming signal being processed by at least one of the processors using at least one of said memory cells; and a linear register array including a plurality of registers operative to store responders arriving from the processors and to provide communication, within a single cycle, between non-adjacent processors processing non-adjacent samples.
Claim 2
Dependent Claim
100 words
Associative signal processing apparatus for processing an incoming signal comprising a plurality of samples, the apparatus comprising: an array of processors, each processor including a multiplicity of content addressable memory (CAM) cells, said array forming a two dimensional array of said content addressable memory cells, each sample of an incoming signal being processed by at least one of the processors using at least one of said memory cells; and a linear register array including a plurality of registers operative to store responders arriving from the processors and to provide communication, within a single cycle, between non-adjacent processors processing non-adjacent samples.
Claim 3
Dependent Claim
19 words
Apparatus according to claim 1 wherein the register array is operative to perform at least one multicell shift operation.
Claim 4
Dependent Claim
12 words
Apparatus according to claim 1 which is operative in video real time.
Claim 5
Dependent Claim
11 words
Apparatus according to claim 1 wherein the signal comprises an image.
Claim 6
Dependent Claim
12 words
Apparatus according to claim 4 wherein the image comprises a color image.
Claim 7
Dependent Claim
19 words
Apparatus according to claim 1 wherein at least one sample is processed by two or more of the processors.
Claim 8
Dependent Claim
17 words
Apparatus according to claim 1 wherein at least one of the processors processes more than one sample.
Claim 9
Dependent Claim
111 words
Associative signal processing apparatus for processing an incoming signal comprising a plurality of samples, the apparatus comprising: an array of processors, each processor including a multiplicity of content addressable memory (CAM) cells, said array forming a two dimensional array of said content addressable memory cells, each sample of an incoming signal being processed by at least one of the processors using at least one of said memory cells; and a linear register array including at least one resister operative to store responders arriving from the processors and to provide communication, within a single cycle, between non-adjacent processors; an I/O buffer register including CAM cells operative to input and output a signal.
Claim 10
Dependent Claim
111 words
Associative signal processing apparatus for processing an incoming signal comprising a plurality of samples, the apparatus comprising: an array of processors, each processor including a multiplicity of content addressable memory (CAM) cells, said array forming a two dimensional array of said content addressable memory cells, each sample of an incoming signal being processed by at least one of the processors using at least one of said memory cells; and a linear register array including at least one resister operative to store responders arriving from the processors and to provide communication, within a single cycle, between non-adjacent processors; an I/O buffer register including CAM cells operative to input and output a signal.
Claim 11
Dependent Claim
23 words
Apparatus according to claim 8 wherein the processor array, the register array and the I/O buffer register are arranged on a single module.
Claim 12
Dependent Claim
24 words
Apparatus according to claim 8 wherein the processor array, the register array and the I/O buffer register are arranged on a single silicon die.
Claim 13
Dependent Claim
24 words
Apparatus according to claim 10 wherein the I/O buffer register includes at least one CAM cell from each processor in said array of processors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-14 | 2002-03-16 | 2002-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-14 | 2006-03-16 | 2006-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-14 | 2010-03-16 | 2010-09-15 | $7700.00 | Window Closed / Lapsed |