Field programmable gate array with high speed SRAM based configurable function block configurable as high performance logic or block of SRAM

Claim 2

A configurable function block comprising: input means for inputting input signals to said configurable function block; output means for outputting output signals from said configurable function block; means for operating said configurable function block as programmable logic to perform at least one predetermined logic operation on said input signals, wherein said means for operating said configurable function block as programmable logic includes a plurality of preconfigured SRAM cells coupled to a plurality of logic gates; means for operating said configurable function block as a block of memory, wherein said means for operating said configurable function block as a block of memory includes means for reading data from, and writing data to, said plurality of preconfigured SRAM cells.

Claim 3

The configurable function block as recited in claim 1, wherein said plurality of logic gates comprises an array of logical "AND" gates.

Claim 4

The configurable function block as recited in claim 2, wherein said plurality of logic gates further comprises an array of logical "OR" gates coupled to said array of logical "AND" gates.

Claim 5

The configurable function block as recited in claim 1, wherein said plurality of preconfigured SRAM cells comprises symmetrical SRAM cells.

Claim 6

The configurable function block as recited in claim 1, wherein said plurality of preconfigured SRAM cells comprises asymmetrical SRAM cells.

Claim 7

The configurable function block as recited in claim 1, wherein said means for operating said configurable function block as programmable logic further comprises a non-volatile architectural element coupled to said plurality of preconfigured SRAM cells.

Claim 8

A configurable function block comprising: input means for inputting input signals to said configurable function block; output means for outputting output signals from said configurable function block; a volatile logic array comprising: a plurality of OR gates, said plurality of OR gates coupled to said output means; a plurality of AND gates, said plurality of AND gates coupled to said plurality of OR gates; switching cell means coupled to said input means and said plurality of AND gates for programmably determining which of said input signals will be coupled to said plurality of AND gates, wherein said switching cell means comprises a plurality of preconfigured SRAM cells; means for operating said volatile logic array as a block of SRAM such that data can be written to, and read from, said plurality of preconfigured SRAM cells.

Claim 9

A configurable function block comprising: input means for inputting input signals to said configurable function block; output means for outputting output signals from said configurable function block; a volatile logic array comprising: a plurality of OR gates, said plurality of OR gates coupled to said output means; a plurality of AND gates, said plurality of AND gates coupled to said plurality of OR gates; switching cell means coupled to said input means and said plurality of AND gates for programmably determining which of said input signals will be coupled to said plurality of AND gates, wherein said switching cell means comprises a plurality of preconfigured SRAM cells; means for operating said volatile logic array as a block of SRAM such that data can be written to, and read from, said plurality of preconfigured SRAM cells.

Claim 10

The configurable function block as recited in claim 7, wherein said plurality of preconfigured SRAM cells comprises symmetrical SRAM cells.

Claim 11

The configurable function block as recited in claim 7, wherein said plurality of preconfigured SRAM cells comprises asymmetrical SRAM cells.

Claim 12

The configurable function block as recited in claim 7, wherein said configurable function block further comprises a non-volatile architectural element coupled to said volatile logic array for programming said switching cell means.

Claim 13

A field programmable gate array with at least one configurable function block configurable by a user of the field programmable gate array as programmable logic or a block of memory, said field programmable gate array comprising: global interconnect matrix means having an input and a first output bus, wherein said global interconnect matrix selectively couples signals from said input to said first output bus; a first configurable function block, coupled to said first output bus of said global interconnect matrix, said first configurable function block comprising: output means for outputting output signals from said first configurable function block; means for operating said first configurable function block as programmable logic to perform at least one predetermined logic operation on said signals coupled to said first configurable function block over said first output bus, wherein said means for operating said first configurable function block as programmable logic includes a first plurality of preconfigured SRAM cells coupled to a first plurality of logic gates; means for operating said first configurable function block as a block of memory, wherein said means for operating said first configurable function block as a block of memory includes means for reading data from, and writing data to, said first plurality of preconfigured SRAM cells.

Claim 14

A field programmable gate array with at least one configurable function block configurable by a user of the field programmable gate array as programmable logic or a block of memory, said field programmable gate array comprising: global interconnect matrix means having an input and a first output bus, wherein said global interconnect matrix selectively couples signals from said input to said first output bus; a first configurable function block, coupled to said first output bus of said global interconnect matrix, said first configurable function block comprising: output means for outputting output signals from said first configurable function block; means for operating said first configurable function block as programmable logic to perform at least one predetermined logic operation on said signals coupled to said first configurable function block over said first output bus, wherein said means for operating said first configurable function block as programmable logic includes a first plurality of preconfigured SRAM cells coupled to a first plurality of logic gates; means for operating said first configurable function block as a block of memory, wherein said means for operating said first configurable function block as a block of memory includes means for reading data from, and writing data to, said first plurality of preconfigured SRAM cells.

Claim 15

The field programmable gate array as recited in claim 11, wherein said first plurality of logic gates comprises an array of logical "AND" gates.

Claim 16

The field programmable gate array as recited in claim 12, wherein said first plurality of logic gates further comprises an array of logical "OR" gates coupled to said array of logical "AND" gates.

Claim 17

The field programmable gate array as recited in claim 11, wherein said first plurality of preconfigured SRAM cells comprise symmetrical SRAM cells.

Claim 18

The field programmable gate array as recited in claim 11, wherein said first plurality of preconfigured SRAM cells comprise asymmetrical SRAM cells.

Claim 19

The field programmable gate array as recited in claim 15, wherein said asymmetrical SRAM cells include a first pass gate and a second pass gate.

Claim 20

The field programmable gate array as recited in claim 11, wherein said means for operating said first configurable function block as programmable logic further comprises a non-volatile architectural element coupled to said first plurality of preconfigured SRAM cells.

Claim 21

The field programmable gate array as recited in claim 11, wherein said global interconnect matrix means further comprises a second output bus and said global interconnect matrix additionally selectively couples signals from said input to said second output bus, and said field programmable gate array further comprises: a second configurable function block, coupled to said second output bus of said global interconnect matrix, said second configurable function block comprising: output means for outputting output signals from said second configurable function block; means for operating said second configurable function block as programmable logic to perform at least one predetermined logic operation on said signals coupled to said second configurable function block over said second output bus, wherein said means for operating said second configurable function block as programmable logic includes a second plurality of preconfigured SRAM cells coupled to a second plurality of logic gates; means for operating said second configurable function block as a block of memory, wherein said means for operating said second configurable function block as a block of memory includes means for reading data from, and writing data to, said second plurality of preconfigured SRAM cells.

Claim 24

The method for operating a configurable function block as provided in claim 19, wherein said programming at least one logical equation into said configurable function block comprises: programming said at least one logical equation into said non-volatile architectural element; transferring said at least one logical equation from said non-volatile architectural element into said plurality of preconfigured SRAM cells.

Claim 25

A computer system comprising: a CPU; a cache memory coupled to said CPU; a programmable logic device coupled to said CPU and said cache memory, said programmable logic device controlling accesses to said cache memory, said programmable logic device comprising: an input for inputting input signals to said programmable logic device; an output for outputting output signals from said programmable logic device; a volatile logic array comprising: a plurality of OR gates, said plurality of OR gates coupled to said output; a plurality of AND gates, said plurality of AND gates coupled to said plurality of OR gates; a plurality of preconfigured SRAM cells coupled to said input and said plurality of AND gates for programmably determining which of said input signals will be coupled to said plurality of AND gates; means for operating said volatile logic array as a block of SRAM such that data can be written to, read from, and stored in said plurality of preconfigured SRAM cells.

Claim 26

A computer system comprising: a CPU; a cache memory coupled to said CPU; a programmable logic device coupled to said CPU and said cache memory, said programmable logic device controlling accesses to said cache memory, said programmable logic device comprising: an input for inputting input signals to said programmable logic device; an output for outputting output signals from said programmable logic device; a volatile logic array comprising: a plurality of OR gates, said plurality of OR gates coupled to said output; a plurality of AND gates, said plurality of AND gates coupled to said plurality of OR gates; a plurality of preconfigured SRAM cells coupled to said input and said plurality of AND gates for programmably determining which of said input signals will be coupled to said plurality of AND gates; means for operating said volatile logic array as a block of SRAM such that data can be written to, read from, and stored in said plurality of preconfigured SRAM cells.

Claim 27

The computer system as recited in claim 21, wherein said plurality of preconfigured SRAM cells comprise symmetrical SRAM cells.

Claim 28

The computer system as recited in claim 22, wherein said plurality of preconfigured SRAM cells comprise asymmetrical SRAM cells.

Claim 29

The computer system as recited in claim 21, wherein said programmable logical device further comprises a non-volatile architectural element coupled to said volatile logic array for programming said switching cell means.

Claim 30

A computer system comprising: CPU means; cache memory means coupled to said CPU means; programmable logic means coupled to said CPU means and said cache memory means, said programmable logic means controlling accesses to said cache memory means, said programmable logic means comprising: input means for inputting input signals to said programmable logic device; output means for outputting output signals from said programmable logic device; volatile logic array means comprising: a plurality of OR gates, said plurality of OR gates coupled to said output means; a plurality of AND gates, said plurality of AND gates coupled to said plurality of OR gates; switching cell means coupled to said input means and said plurality of AND gates for programmably determining which of said input signals will be coupled to said plurality of AND gates, wherein said switching cell means comprises a plurality of preconfigured SRAM cells; means for operating said volatile logic array as a block of SRAM such that data can be written to, and read from, and stored in said plurality of preconfigured SRAM cells.

Claim 31

A computer system comprising: CPU means; cache memory means coupled to said CPU means; programmable logic means coupled to said CPU means and said cache memory means, said programmable logic means controlling accesses to said cache memory means, said programmable logic means comprising: input means for inputting input signals to said programmable logic device; output means for outputting output signals from said programmable logic device; volatile logic array means comprising: a plurality of OR gates, said plurality of OR gates coupled to said output means; a plurality of AND gates, said plurality of AND gates coupled to said plurality of OR gates; switching cell means coupled to said input means and said plurality of AND gates for programmably determining which of said input signals will be coupled to said plurality of AND gates, wherein said switching cell means comprises a plurality of preconfigured SRAM cells; means for operating said volatile logic array as a block of SRAM such that data can be written to, and read from, and stored in said plurality of preconfigured SRAM cells.

Claim 32

The computer system as recited in claim 25, wherein said plurality of preconfigured SRAM cells comprise symmetrical SRAM cells.

Claim 33

The computer system as recited in claim 26, wherein said plurality of preconfigured SRAM cells comprise asymmetrical SRAM cells.

Claim 34

The computer system as recited in claim 25, wherein said programmable logical device further comprises a non-volatile architectural element coupled to said volatile logic array means for programming said switching cell means.