Patent US5808932A successfully refreshed from Google Patents.
US5808932A
Expired / Lapsed
US
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Memory system which enables storage and retrieval of more than two states in a memory cell
Assignee: Nippon Furnace Co Ltd
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Filing: 1996-12-23
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Granted: 1998-09-15
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Expires: 2016-12-23
Abstract
Abstract A memory circuit which enables storage of more than two logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit. The disclosed memory circuit comprises an analog-to-digital converter coupled to detect a current through a transistor in a memory cell. The current is determined by a charge stored on the transistor's gate. By enabling the current to be detected in discrete increments, it becomes possible to represent more than one bit of information with the charge stored in the memory cell. Usage of additional increments necessitates more precise storage and detection circuitry. In one embodiment, the storage circuitry uses feedback to obtain a greater logic state retrieval accuracy.
Inventors
- 👤 V. Swamy Irrinki
- 👤 Ashok Kapoor
- 👤 Raymond T. Leung
- 👤 Alex Owens
- 👤 Thomas R. Wik
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 22:25
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/56; G11C11/565; G11C7/00; G11C7/16
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
123 words
A memory circuit comprising: a memory cell which includes: a storage transistor with a first terminal, a second terminal, and a gate, said first terminal coupled to a predetermined voltage; a read transistor coupled to said second terminal, said read transistor configured to conduct a current through said storage transistor when a read signal is asserted; and a write transistor coupled to said gate, said write transistor configured to store a charge on said gate of said storage transistor when a write signal is asserted; and an analog-to-digital converter coupled to detect a value indicative of a voltage across said storage transistor, wherein said analog to digital converter is configured to convert said value to one of at least three distinct digital values.
Claim 2
Dependent Claim
123 words
A memory circuit comprising: a memory cell which includes: a storage transistor with a first terminal, a second terminal, and a gate, said first terminal coupled to a predetermined voltage; a read transistor coupled to said second terminal, said read transistor configured to conduct a current through said storage transistor when a read signal is asserted; and a write transistor coupled to said gate, said write transistor configured to store a charge on said gate of said storage transistor when a write signal is asserted; and an analog-to-digital converter coupled to detect a value indicative of a voltage across said storage transistor, wherein said analog to digital converter is configured to convert said value to one of at least three distinct digital values.
Claim 3
Dependent Claim
30 words
The memory circuit of claim 1, wherein said analog-to-digital converter comprises a plurality of comparators, each coupled to compare said input voltage to one of a plurality of reference voltages.
Claim 4
Dependent Claim
36 words
The memory circuit of claim 1, further comprising a data line driver coupled to receive one of said distinct digital values, said data line driver configured to responsively provide a write voltage to said write transistor.
Claim 5
Dependent Claim
60 words
The memory circuit of claim 1, further comprising a data level controller coupled to receive one of said distinct digital values, said data level controller is configured to receive said input voltage as a feedback signal and, in accordance with said distinct digital value, to adjust said write voltage to cause said feedback signal to converge upon a predetermined value.
Claim 6
Dependent Claim
27 words
The memory circuit of claim 3, wherein said write voltage is one of a set of equally spaced voltage levels which correspond to said distinct digital values.
Claim 7
Dependent Claim
27 words
The memory circuit of claim 4 wherein said desired voltage is one of a set of equally spaced voltage levels which correspond to said distinct digital values.
Claim 8
Dependent Claim
28 words
The memory circuit of claim 1, further comprising an address decoder configured to assert said read signal in response to receiving an address signal and an enable signal.
Claim 9
Dependent Claim
66 words
The memory circuit of claim 1, further comprising a bi-directional gate configured to convert n binary data bits into m logic signals during a write operation, wherein each of said logic signals has one of said distinct digital values, said bi-directional gate further configured to convert m logic signals, each having one of said distinct digital values, into n binary data bits during a read operation.
Claim 10
Dependent Claim
30 words
The memory circuit of claim 1, further comprising a sense amplifier coupled to detect said current through said storage transistor, said sense amplifier configured to responsively provide said input voltage.
Claim 11
Dependent Claim
25 words
The memory circuit of claim 1, wherein said analog to digital converter is configured to convert said value to one of three distinct digital values.
Claim 12
Dependent Claim
25 words
The memory circuit of claim 1, wherein said analog to digital converter is configured to convert said value to one of four distinct digital values.
Claim 13
Dependent Claim
297 words
A memory circuit comprising: an address decoder configured to assert a word read signal in response to receiving an address signal, a read signal, and an enable signal, said address decoder further configured to assert a word write signal in response to said address signal, a write signal, and said enable signal; a bi-directional gate configured to convert n binary data bits into m logic signals during a write operation, wherein each of said logic signals has one of a number of distinct digital values, said number is at least three, said bi-directional gate further configured to convert m logic signals, each having one of said distinct digital values, into n binary data bits during a read operation; a memory cell which includes: a storage transistor with a first terminal, a second terminal, and a gate, said first terminal coupled to a predetermined voltage; a read transistor coupled to said second terminal, said read transistor configured to conduct a current through said storage transistor when said word read signal is asserted; and a write transistor coupled to said gate, said write transistor configured to store a charge on said gate of said storage transistor when said word write signal is asserted; a data line driver coupled to receive one of said number of distinct digital values, said data line driver configured to responsively provide a write voltage to said write transistor; a sense amplifier coupled to detect a voltage indicative of said current through said storage transistor, said sense amplifier configured to responsively provide an input voltage; and an analog-to-digital converter coupled to detect said input voltage indicative of a voltage across said storage transistor, wherein said analog to digital converter is configured to convert said input voltage to one of at least three distinct digital values.
Claim 14
Dependent Claim
297 words
A memory circuit comprising: an address decoder configured to assert a word read signal in response to receiving an address signal, a read signal, and an enable signal, said address decoder further configured to assert a word write signal in response to said address signal, a write signal, and said enable signal; a bi-directional gate configured to convert n binary data bits into m logic signals during a write operation, wherein each of said logic signals has one of a number of distinct digital values, said number is at least three, said bi-directional gate further configured to convert m logic signals, each having one of said distinct digital values, into n binary data bits during a read operation; a memory cell which includes: a storage transistor with a first terminal, a second terminal, and a gate, said first terminal coupled to a predetermined voltage; a read transistor coupled to said second terminal, said read transistor configured to conduct a current through said storage transistor when said word read signal is asserted; and a write transistor coupled to said gate, said write transistor configured to store a charge on said gate of said storage transistor when said word write signal is asserted; a data line driver coupled to receive one of said number of distinct digital values, said data line driver configured to responsively provide a write voltage to said write transistor; a sense amplifier coupled to detect a voltage indicative of said current through said storage transistor, said sense amplifier configured to responsively provide an input voltage; and an analog-to-digital converter coupled to detect said input voltage indicative of a voltage across said storage transistor, wherein said analog to digital converter is configured to convert said input voltage to one of at least three distinct digital values.
Claim 15
Dependent Claim
60 words
The memory circuit of claim 12, wherein said analog-to-digital converter comprises a number of comparators, each coupled to compare said input voltage to one of a number of reference voltages, wherein said number of comparators equals said number of reference voltages, and wherein said number of reference voltages is equal to one less than said number of distinct digital values.
Claim 16
Dependent Claim
41 words
The memory circuit of claim 12, wherein said data line driver is further coupled to receive said input voltage, said data line driver is configured to adjust said write voltage to cause said input voltage to converge to a desired voltage.
Claim 17
Dependent Claim
310 words
A computer system comprising: a CPU coupled to communicate address and data information on a bus; and a memory circuit coupled to store and retrieve said data information, said memory circuit includes: an address decoder configured to assert a word read signal in response to receiving an address signal, a read signal, and an enable signal, said address decoder further configured to assert a word write signal in response to said address signal, a write signal, and said enable signal; a bi-directional gate configured to convert n binary data bits into m logic signals during a write operation, wherein each of said logic signals has one of a number of distinct digital values, said number is at least three, said bi-directional gate further configured to convert m logic signals, each having one of said distinct digital values, into n binary data bits during a read operation; a memory cell which includes: a storage transistor with a first terminal, a second terminal, and a gate, said first terminal coupled to a known voltage; a read transistor coupled to said second terminal, said read transistor configured to conduct a current through said storage transistor when said word read signal is asserted; and a write transistor coupled to said gate, said write transistor configured to store a charge on said gate of said storage transistor when said word write signal is asserted; a data line driver coupled to receive one of said number of distinct digital values, said data line driver configured to responsively provide a write voltage to said write transistor; a sense amplifier coupled to detect a voltage indicative of said current through said storage transistor, said sense amplifier configured to responsively provide an input voltage; and an analog-to-digital converter coupled to detect said input voltage and configured to convert said value to one of at least three distinct digital values.
Claim 18
Dependent Claim
310 words
A computer system comprising: a CPU coupled to communicate address and data information on a bus; and a memory circuit coupled to store and retrieve said data information, said memory circuit includes: an address decoder configured to assert a word read signal in response to receiving an address signal, a read signal, and an enable signal, said address decoder further configured to assert a word write signal in response to said address signal, a write signal, and said enable signal; a bi-directional gate configured to convert n binary data bits into m logic signals during a write operation, wherein each of said logic signals has one of a number of distinct digital values, said number is at least three, said bi-directional gate further configured to convert m logic signals, each having one of said distinct digital values, into n binary data bits during a read operation; a memory cell which includes: a storage transistor with a first terminal, a second terminal, and a gate, said first terminal coupled to a known voltage; a read transistor coupled to said second terminal, said read transistor configured to conduct a current through said storage transistor when said word read signal is asserted; and a write transistor coupled to said gate, said write transistor configured to store a charge on said gate of said storage transistor when said word write signal is asserted; a data line driver coupled to receive one of said number of distinct digital values, said data line driver configured to responsively provide a write voltage to said write transistor; a sense amplifier coupled to detect a voltage indicative of said current through said storage transistor, said sense amplifier configured to responsively provide an input voltage; and an analog-to-digital converter coupled to detect said input voltage and configured to convert said value to one of at least three distinct digital values.
Claim 19
Dependent Claim
60 words
The computer system of claim 15, wherein said analog-to-digital converter comprises a number of comparators, each coupled to compare said input voltage to one of a number of reference voltages, wherein said number of comparators equals said number of reference voltages, and wherein said number of reference voltages is equal to one less than said number of distinct digital values.
Claim 20
Dependent Claim
41 words
The computer system of claim 15, wherein said data line driver is further coupled to receive said input voltage, said data line driver is configured to adjust said write voltage to cause said input voltage to converge to a desired voltage.
Claim 21
Dependent Claim
15 words
The computer system of claim 15, wherein said number of distinct digital values is five.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-09-14 | 2002-03-16 | 2002-09-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-09-14 | 2006-03-16 | 2006-09-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-09-14 | 2010-03-16 | 2010-09-15 | $7700.00 | Window Closed / Lapsed |