Programmable bandwidth I/O port and a communication interface using the same port having a plurality of serial access memories capable of being configured for a variety of protocols

Claim 2

A communications interface having a plurality of I/O ports each of which has a programmable bandwidth for allowing asynchronous data transfer through said plurality of ports, said communications interface comprising: a random access memory having a data bus containing a predetermined number of bits; a plurality of serial access memories each of which has a plurality of memory cells, the corresponding memory cells of each serial access memory being connected to a respective bit of said random access memory data bus to allow data transfer between said random access memory and the memory of cells of said serial access memory responsive to respective transfer signals, the memory cells in groups of one or more of said serial access memories being selectively connected to respective of said I/O ports responsive to negative sequence signals; a random access memory transfer circuit providing said transfer signals as a function of the programming of said I/O port so that data is transferred between said random access memory and selected memory cells of selected serial access memories as a function of said programming, said random access memory transfer circuit comprising: a transfer enable signal generator included in said random access memory, said transfer enable signal generator generating transfer enable signals corresponding to each of said serial access memories; a program generator providing programming signals designating each serial access memory to be used with a respective I/O port and the bandwidth of such I/O port; and a logic circuit receiving said transfer enable signals and said programming signals, said logic circuit generating said transfer signals as a predetermined function of said transfer enable signals and said programming signals, said transfer signals transferring data between said random access memory and at least one serial access memories when a transfer enable signal corresponding to said serial access memory is generated and a programming signal corresponding to an I/O port connected to said serial access memory is generated; and a sequencer providing said sequence signals as a function of said programming so that data is transferred between said I/O ports and selected memory cells of selected serial access memories as a function of said programming.

Claim 3

A communications interface having a plurality of I/O ports each of which has a programmable bandwidth for allowing asynchronous data transfer through said plurality of ports, said communications interface comprising: a random access memory having a data bus containing a predetermined number of bits; a plurality of serial access memories each of which has a plurality of memory cells, the corresponding memory cells of each serial access memory being connected to a respective bit of said random access memory data bus to allow data transfer between said random access memory and the memory of cells of said serial access memory responsive to respective transfer signals, the memory cells in groups of one or more of said serial access memories being selectively connected to respective of said I/O ports responsive to negative sequence signals; a random access memory transfer circuit providing said transfer signals as a function of the programming of said I/O port so that data is transferred between said random access memory and selected memory cells of selected serial access memories as a function of said programming; and a sequencer providing said sequence signals as a function of said programming so that data is transferred between said I/O ports and selected memory cells of selected serial access memories as a function of said programming, said sequencer comprising: a program generator providing programming signals designating each serial access memory to be used with a respective I/O port and the bandwidth of such I/O port and the bandwidth of such I/O port; a counter circuit for each of said serial access memories, said counter circuits receiving said programming signals and generating a binary output incrementing in a pattern corresponding to the order in which the memory cells of said serial access memory are to communicate with said I/O port, the increment pattern being designated by said programming signals; and a binary decoder having a plurality of outputs corresponding in number to the memory cells of said serial access memory said decoder receiving the binary output of said counter circuit and generating at its output said sequence signals.

Claim 4

A communications interface having a plurality of I/O ports each of which has a programmable bandwidth for allowing asynchronous data transfer through said plurality of ports, said communications interface comprising: a random access memory having a data bus containing a predetermined number of bits; a plurality of serial access memories each of which has a plurality of memory cells, the corresponding memory cells of each serial access memory being connected to a respective bit of said random access memory data bus to allow data transfer between said random access memory and the memory of cells of said serial access memory responsive to respective transfer signals, the memory cells in groups of one or more of said serial access memories being selectively connected to respective of said I/O ports responsive to negative sequence signals; a random access memory transfer circuit providing said transfer signals as a function of the programming of said I/O port so that data is transferred between said random access memory and selected memory cells of selected serial access memories as a function of said programming; and a sequencer providing said sequence signals as a function of said programming so that data is transferred between said I/O ports and selected memory cells of selected serial access memories as a function of said programming, said sequencer comprising: a program generator providing programming signals designating each serial access memory to be used with a respective I/O port and the bandwidth of such I/O port and the bandwidth of such I/O port; a counter circuit for each of said serial access memories, said counter circuits receiving said programming signals and generating a binary output incrementing in a pattern corresponding to the order in which the memory cells of said serial access memory are to communicate with said I/O port, the increment pattern being designated by said programming signals; and a binary decoder having a plurality of outputs corresponding in number to the memory cells of said serial access memory said decoder receiving the binary output of said counter circuit and generating at its output said sequence signals.

Claim 5

The communications interface of claim 2 wherein said counter circuit includes a plurality of flip-flops connected to each other to implement a counter, and wherein said programming signals are applied to respective force inputs of said counters to selectively force the outputs of said counters to predetermined values depending upon the state of said programming signals.

Claim 6

A multiple port communications interface for allowing asynchronous communications between a first communications port and a plurality of second communication ports, comprising: a random access memory having a data bus containing a predetermined number of bits; a first plurality of serial access memories each of which has a plurality of memory cells communicating with a respective bit of said random access memory data bus to allow data transfer between said random access memory and the memory cells of said serial access memory responsive to respective transfer signals, the memory cells in groups of one or more of said serial access memories being selectively connected to said first communications port for allowing data transfer between said first communications port and said first plurality of serial access memories responsive to respective sequence signals; a second plurality of serial access memories each of which has a plurality of memory cells communicating with said data bus to allow data transfer between said random access memory and the memory cells of said serial access memory responsive to respective transfer signals, the memory cells in groups of one or more of said serial access memories being selectively connected to respective second communications ports for allowing data transfer between said second communications ports and said serial access memories responsive to respective sequence signals; a random access memory transfer circuit providing said transfer signals as a function of the bandwidth of each of said communications ports and, said random access memory transfer circuit comprising: a transfer enable signal generator included in said random access memory, said transfer enable signal generator generating transfer enable signals corresponding to each of said serial access memories; a program generator providing programming signals designating each serial access memory to be used with a respective I/O port and the bandwidth of such I/O port; and a logic circuit receiving said transfer enable signals and said programming signals, said logic circuit generating said transfer signals as a predetermined function of said transfer enable signals and said programming signals, said transfer signals transferring data between said random access memory and at least one serial access memories when a transfer enable signal corresponding to said serial access memory is generated and a programming signal corresponding to an I/O port connected to said serial access memory is generated; and a sequencer providing said sequence signals as a function of the bandwidth of each of said communications ports.

Claim 7

A multiple port communications interface for allowing asynchronous communications between a first communications port and a plurality of second communication ports, comprising: a random access memory having a data bus containing a predetermined number of bits; a first plurality of serial access memories each of which has a plurality of memory cells communicating with a respective bit of said random access memory data bus to allow data transfer between said random access memory and the memory cells of said serial access memory responsive to respective transfer signals, the memory cells in groups of one or more of said serial access memories being selectively connected to said first communications port for allowing data transfer between said first communications port and said first plurality of serial access memories responsive to respective sequence signals; a second plurality of serial access memories each of which has a plurality of memory cells communicating with said data bus to allow data transfer between said random access memory and the memory cells of said serial access memory responsive to respective transfer signals, the memory cells in groups of one or more of said serial access memories being selectively connected to respective second communications ports for allowing data transfer between said second communications ports and said serial access memories responsive to respective sequence signals; a random access memory transfer circuit providing said transfer signals as a function of the bandwidth of each of said communications ports and, said random access memory transfer circuit comprising: a transfer enable signal generator included in said random access memory, said transfer enable signal generator generating transfer enable signals corresponding to each of said serial access memories; a program generator providing programming signals designating each serial access memory to be used with a respective I/O port and the bandwidth of such I/O port; and a logic circuit receiving said transfer enable signals and said programming signals, said logic circuit generating said transfer signals as a predetermined function of said transfer enable signals and said programming signals, said transfer signals transferring data between said random access memory and at least one serial access memories when a transfer enable signal corresponding to said serial access memory is generated and a programming signal corresponding to an I/O port connected to said serial access memory is generated; and a sequencer providing said sequence signals as a function of the bandwidth of each of said communications ports.

Claim 8

A multiple port communications interface for allowing asynchronous communications between a first communications port and a plurality of second communication ports, comprising: a random access memory having a data bus containing a predetermined number of bits; a first plurality of serial access memories each of which has a plurality of memory cells communicating with a respective bit of said random access memory data bus to allow data transfer between said random access memory and the memory cells of said serial access memory responsive to respective transfer signals the memory cells in groups of one or more of said serial access memories being selectively connected to said first communications port for allowing data transfer between said first communications port and said first plurality of serial access memories responsive to respective sequence signals; a second plurality of serial access memories each of which has a plurality of memory cells communicating with said data bus to allow data transfer between said random access memory and the memory cells of said serial access memory responsive to respective transfer signals the memory cells in groups of one or more of said serial access memories being selectively connected to respective second communications ports for allowing data transfer between said second communications ports and said serial access memories responsive to respective sequence signals; a random access memory transfer circuit providing said transfer signals as a function of the bandwidth of each of said communications ports; and a sequencer providing said sequence signals as a function of the bandwidth of each of said communications ports, said sequencer comprising: a program generator providing programming signals designating each serial access memory to be used with a respective I/O port and the bandwidth of such I/O port; a counter circuit for each of said serial access memories, said counter circuits receiving said programming signals and generating a binary output incrementing in a pattern corresponding to the order in which the memory cells of said serial access memory are to communicate with said I/O port, the increment pattern being designated by said programming signals; and a binary decoder having a plurality of outputs corresponding in number to the memory cells of said serial access memory, said decoder receiving the binary output of said counter circuit and generating at its output said sequence signals.

Claim 9

A multiple port communications interface for allowing asynchronous communications between a first communications port and a plurality of second communication ports, comprising: a random access memory having a data bus containing a predetermined number of bits; a first plurality of serial access memories each of which has a plurality of memory cells communicating with a respective bit of said random access memory data bus to allow data transfer between said random access memory and the memory cells of said serial access memory responsive to respective transfer signals the memory cells in groups of one or more of said serial access memories being selectively connected to said first communications port for allowing data transfer between said first communications port and said first plurality of serial access memories responsive to respective sequence signals; a second plurality of serial access memories each of which has a plurality of memory cells communicating with said data bus to allow data transfer between said random access memory and the memory cells of said serial access memory responsive to respective transfer signals the memory cells in groups of one or more of said serial access memories being selectively connected to respective second communications ports for allowing data transfer between said second communications ports and said serial access memories responsive to respective sequence signals; a random access memory transfer circuit providing said transfer signals as a function of the bandwidth of each of said communications ports; and a sequencer providing said sequence signals as a function of the bandwidth of each of said communications ports, said sequencer comprising: a program generator providing programming signals designating each serial access memory to be used with a respective I/O port and the bandwidth of such I/O port; a counter circuit for each of said serial access memories, said counter circuits receiving said programming signals and generating a binary output incrementing in a pattern corresponding to the order in which the memory cells of said serial access memory are to communicate with said I/O port, the increment pattern being designated by said programming signals; and a binary decoder having a plurality of outputs corresponding in number to the memory cells of said serial access memory, said decoder receiving the binary output of said counter circuit and generating at its output said sequence signals.

Claim 10

A variable bandwidth I/O port, comprising: a random access memory having a data bus containing a predetermined number of bits; a plurality of serial access memories each of which has a plurality of memory cells, the corresponding memory cells of each serial access memory being connected to a respective bit of said random access memory data bus to allow data transfer between said random access memory and the memory cells of said serial access memory responsive to respective transfer signals, the memory cells in groups of one or more of said serial access memories being selectively connected to respective I/O port lines of said I/O port responsive to respective sequence signals; a random access memory transfer circuit providing said transfer signals as a function of the programming of said I/O port so that data is transferred between said random access memory and selected memory cells of selected serial access memories as a function of said programming, said random access memory transfer circuit comprising: a transfer enable signal generator included in said random access memory, said transfer enable signal generator generating transfer enable signals corresponding to each of said serial access memories; a program generator providing programming signals designating each serial access memory to be used with a respective I/O port and the bandwidth of such I/O port; and a logic circuit receiving said transfer enable signals and said programming signals, said logic circuit generating said transfer signals as a predetermined function of said transfer enable signals and said programming signals, said transfer signals transferring data between said random access memory and at least one serial access memories when a transfer enable signal corresponding to said serial access memory is generated and a programming signal corresponding to an I/O port connected to said serial access memory is generated; and a sequencer providing said sequence signals as a function of said programming so that data is transferred between selected memory cells of selected serial access memories and respective number of lines of said I/O port corresponding to said programming.

Claim 11

A variable bandwidth I/O port, comprising: a random access memory having a data bus containing a predetermined number of bits; a plurality of serial access memories each of which has a plurality of memory cells, the corresponding memory cells of each serial access memory being connected to a respective bit of said random access memory data bus to allow data transfer between said random access memory and the memory cells of said serial access memory responsive to respective transfer signals, the memory cells in groups of one or more of said serial access memories being selectively connected to respective I/O port lines of said I/O port responsive to respective sequence signals; a random access memory transfer circuit providing said transfer signals as a function of the programming of said I/O port so that data is transferred between said random access memory and selected memory cells of selected serial access memories as a function of said programming, said random access memory transfer circuit comprising: a transfer enable signal generator included in said random access memory, said transfer enable signal generator generating transfer enable signals corresponding to each of said serial access memories; a program generator providing programming signals designating each serial access memory to be used with a respective I/O port and the bandwidth of such I/O port; and a logic circuit receiving said transfer enable signals and said programming signals, said logic circuit generating said transfer signals as a predetermined function of said transfer enable signals and said programming signals, said transfer signals transferring data between said random access memory and at least one serial access memories when a transfer enable signal corresponding to said serial access memory is generated and a programming signal corresponding to an I/O port connected to said serial access memory is generated; and a sequencer providing said sequence signals as a function of said programming so that data is transferred between selected memory cells of selected serial access memories and respective number of lines of said I/O port corresponding to said programming.

Claim 12

A variable bandwidth I/O port, comprising: a random access memory having a data bus containing a predetermined number of bits; a plurality of serial access memories each of which has a plurality of memory cells, the corresponding memory cells of each serial access memory being connected to a respective bit of said random access memory data bus to allow data transfer between said random access memory and the memory cells of said serial access memory responsive to respective transfer signals, the memory cells in groups of one or more of said serial access memories being selectively connected to respective I/O port lines of said I/O port responsive to respective sequence signals; a random access memory transfer circuit providing said transfer signals as a function of the programming of said I/O port so that data is transferred between said random access memory and selected memory cells of selected serial access memories as a function of said programming; and a sequencer providing said sequence signals as a function of said programming so that data is transferred between selected memory cells of selected serial access memories and respective number of lines of said I/O port corresponding to said programming, said sequencer comprising: a program generator providing programming signals designating each serial access memory to be used with a respective I/O port and the bandwidth of such I/O port; a counter circuit for each of said serial access memories, said counter circuits receiving said programming signals and generating a binary output incrementing in a pattern corresponding to the order in which the memory cells of said serial access memory are to communicate with said I/O port, the increment pattern being designated by said programming signals; and a binary decoder having a plurality of outputs corresponding in number to the memory cells of said serial access memory, said decoder receiving the binary output of said counter circuit and generating at its output said sequence signals.

Claim 13

A variable bandwidth I/O port, comprising: a random access memory having a data bus containing a predetermined number of bits; a plurality of serial access memories each of which has a plurality of memory cells, the corresponding memory cells of each serial access memory being connected to a respective bit of said random access memory data bus to allow data transfer between said random access memory and the memory cells of said serial access memory responsive to respective transfer signals, the memory cells in groups of one or more of said serial access memories being selectively connected to respective I/O port lines of said I/O port responsive to respective sequence signals; a random access memory transfer circuit providing said transfer signals as a function of the programming of said I/O port so that data is transferred between said random access memory and selected memory cells of selected serial access memories as a function of said programming; and a sequencer providing said sequence signals as a function of said programming so that data is transferred between selected memory cells of selected serial access memories and respective number of lines of said I/O port corresponding to said programming, said sequencer comprising: a program generator providing programming signals designating each serial access memory to be used with a respective I/O port and the bandwidth of such I/O port; a counter circuit for each of said serial access memories, said counter circuits receiving said programming signals and generating a binary output incrementing in a pattern corresponding to the order in which the memory cells of said serial access memory are to communicate with said I/O port, the increment pattern being designated by said programming signals; and a binary decoder having a plurality of outputs corresponding in number to the memory cells of said serial access memory, said decoder receiving the binary output of said counter circuit and generating at its output said sequence signals.