Hot reconfigurable parallel bus bridging circuit

Claim 2

For use in a computer system having a CPU and a first parallel bus system, a reprogrammable adaptor circuit for bridging the first parallel bus system to a second parallel bus system, wherein the first bus system is not directly compatible with the second bus system, said adaptor circuit comprising: a bridging circuit responsive to configuration programming information for bridging a communication path between the first bus system and the second bus system; a memory storage device for storing said configuration programming information used to configure said bridging circuit; programming means for applying said configuration programming information to configure said bridging circuit to establish said bridged communication path; and means in communication with the CPU for changing the configuration programming information stored within said memory storage device while the computer system is operating, without physically removing the storage device or the bridging circuit from the adaptor circuit, thereby hotly reconfiguring said bridging circuit, wherein the changed configuration information allows the bridging circuit to bridge a communication path between the first bus system and a third parallel bus system, the third parallel bus system being of a different type than the second parallel bus system.

Claim 3

The circuit of claim 1, wherein said programming means comprises means for preventing access to said bridging circuit while said bridging circuit is being configured by said programming means, and for allowing access to said bridging circuit after said bridging circuit has been configured; and wherein said changing means comprises a plurality of registers for latching at least a portion of said changed configuration information to facilitate the changing of configuration program information stored within said memory storage device.

Claim 4

The circuit of claim 1 wherein said changing means includes means for writing data and address information into said storage device without removing the storage device from the computer system.

Claim 5

The circuit of claim 1 wherein said memory storage device comprises an EEPROM.

Claim 6

The circuit of claim 1 wherein said memory storage device comprises a slave microprocessor and memory storage componentry.

Claim 7

The circuit of claim 1 wherein said first bus system is a PCMCIA compatible bus.

Claim 8

A computer system for communicating between a first parallel bus system and a second parallel bus system, wherein the first bus system is not directly compatible with the second bus system, said computer system comprising: a CPU; at least one peripheral port for providing a communication path between the first parallel bus system and the second parallel bus system; a reconfigurable adaptor circuit connected to said peripheral port for bridging the communication path between the first parallel bus system and the second parallel bus system; and means in communication with said CPU for hotly reconfiguring said adaptor circuit while the computer system is operating, without physically removing the adaptor circuit from the computer system to enable the adaptor circuit to bridge a communication path between the first bus system and a third parallel bus system, the third parallel bus system being of a different type than the second parallel bus system.

Claim 9

A computer system for communicating between a first parallel bus system and a second parallel bus system, wherein the first bus system is not directly compatible with the second bus system, said computer system comprising: a CPU; at least one peripheral port for providing a communication path between the first parallel bus system and the second parallel bus system; a reconfigurable adaptor circuit connected to said peripheral port for bridging the communication path between the first parallel bus system and the second parallel bus system; and means in communication with said CPU for hotly reconfiguring said adaptor circuit while the computer system is operating, without physically removing the adaptor circuit from the computer system to enable the adaptor circuit to bridge a communication path between the first bus system and a third parallel bus system, the third parallel bus system being of a different type than the second parallel bus system.

Claim 10

The circuit of claim 7 wherein said reconfiguring means comprises: means for preventing access to said adaptor circuit while said adaptor circuit is being reconfigured by said reconfiguring means, and for allowing access to said adaptor circuit after said adaptor circuit has been reconfigured; and a plurality of registers for latching configuration information related to the reconfiguring of said adaptor circuit to facilitate the reconfiguring of said adaptor circuit.

Claim 11

The circuit of claim 7 wherein said reconfiguring means comprises a memory storage device for storing configuration information used to reconfigure said adaptor circuit.

Claim 12

The circuit of claim 9 wherein said memory storage device comprises an EEPROM.

Claim 13

The circuit of claim 9 wherein said memory storage device comprises a slave microprocessor and memory storage componentry.

Claim 14

The computer system of claim 9 wherein said reconfiguring means further comprises means for writing data and address information into said storage device without removing the storage device from the computer system.

Claim 15

The circuit of claim 7 wherein said first bus system is a PCMCIA compatible bus.

Claim 16

In a computer system comprising a CPU, a first parallel bus system, at least one peripheral port, and a reconfigurable bridging circuit connected to the peripheral port for bridging a communication path between the first parallel bus system and a plurality of other parallel bus systems which are not directly compatible with the first bus system, wherein the plurality of other parallel bus systems includes a second parallel bus system and a third parallel bus system, a method for communicating between the first bus system and at least one of the plurality of other bus systems via the peripheral port and bridging circuit, said method comprising the steps of: (a) configuring the bridging circuit to bridge a communication path between the first bus system and the second bus system without physically removing said bridging circuit from the computer system; (b) communicating data between the first bus system and the second bus systems via the peripheral port and configured bridging circuit; (c) hotly reconfiguring the bridging circuit to bridge a communication path between the first bus system and the third bus system, while the computer system is operating, without physically removing said bridging circuit from the computer system; and (d) communicating data between the first bus system and the third bus systems via the peripheral port and reconfigured bridging circuit the third parallel bus system being of a different type than the second parallel bus system.

Claim 17

In a computer system comprising a CPU, a first parallel bus system, at least one peripheral port, and a reconfigurable bridging circuit connected to the peripheral port for bridging a communication path between the first parallel bus system and a plurality of other parallel bus systems which are not directly compatible with the first bus system, wherein the plurality of other parallel bus systems includes a second parallel bus system and a third parallel bus system, a method for communicating between the first bus system and at least one of the plurality of other bus systems via the peripheral port and bridging circuit, said method comprising the steps of: (a) configuring the bridging circuit to bridge a communication path between the first bus system and the second bus system without physically removing said bridging circuit from the computer system; (b) communicating data between the first bus system and the second bus systems via the peripheral port and configured bridging circuit; (c) hotly reconfiguring the bridging circuit to bridge a communication path between the first bus system and the third bus system, while the computer system is operating, without physically removing said bridging circuit from the computer system; and (d) communicating data between the first bus system and the third bus systems via the peripheral port and reconfigured bridging circuit the third parallel bus system being of a different type than the second parallel bus system.

Claim 18

The method of claim 14 further including the steps of: asserting a BUSY signal to the CPU during at least a portion of time when the bridging circuit is being reconfigured to prevent access to said bridging circuit, and asserting a READY signal to the CPU during at least a portion of time when the bridging circuit is not being reconfigured to allow access to said bridging circuit.

Claim 19

The method of claim 14 wherein steps (a) and (c) each include the step of configuring the bridging circuit to bridge a communication path between a PCMCIA bus system and the second bus system without removing the bridging circuit from the computer system.

Claim 20

In a computer system comprising a CPU, a first parallel bus system, at least one peripheral port, and a reconfigurable bridging circuit connected to the peripheral port for bridging a communication path between the first parallel bus system and a plurality of other parallel bus systems not directly compatible with the first bus system, said computer system further comprising a memory storage device for storing configuration programming information used to configure the bridging circuit to bridge the first bus system with at least one of the plurality of other bus systems, a method for establishing a communication path between the first bus system and one of the plurality of other bus systems via the peripheral port and bridging circuit, said method comprising the steps of: (a) storing configuration programming information in the memory storage device, while the computer system is operating, without physically removing the storage device from the computer system; (b) hotly configuring the bridging circuit, using the stored configuration programming information, while the computer system is operating, to bridge a communication path between the first bus system and a second bus system of the plurality of other bus systems without removing the bridging circuit from the computer system; and (c) establishing a communication path between the first bus system and the second bus system via the peripheral port and bridging circuit, enabling an exchange of information to take place between the two parallel bus systems, the third parallel bus system being of a different type than the second parallel bus system.

Claim 21

In a computer system comprising a CPU, a first parallel bus system, at least one peripheral port, and a reconfigurable bridging circuit connected to the peripheral port for bridging a communication path between the first parallel bus system and a plurality of other parallel bus systems not directly compatible with the first bus system, said computer system further comprising a memory storage device for storing configuration programming information used to configure the bridging circuit to bridge the first bus system with at least one of the plurality of other bus systems, a method for establishing a communication path between the first bus system and one of the plurality of other bus systems via the peripheral port and bridging circuit, said method comprising the steps of: (a) storing configuration programming information in the memory storage device, while the computer system is operating, without physically removing the storage device from the computer system; (b) hotly configuring the bridging circuit, using the stored configuration programming information, while the computer system is operating, to bridge a communication path between the first bus system and a second bus system of the plurality of other bus systems without removing the bridging circuit from the computer system; and (c) establishing a communication path between the first bus system and the second bus system via the peripheral port and bridging circuit, enabling an exchange of information to take place between the two parallel bus systems, the third parallel bus system being of a different type than the second parallel bus system.

Claim 22

The method of claim 17 wherein said storing step (a) comprises the step of writing data and address information into the memory storage device without physically removing the storage device from the computer system.

Claim 23

The method of claim 17 further comprising the steps of: changing the configuration programming information in the memory storage device without physically removing the storage device from the computer system; reconfiguring the bridging circuit, using the changed configuration programming information, to bridge a communication path between the first parallel bus system and a third bus system of the plurality of other bus systems without removing the bridging circuit from the computer system; and establishing a communication path between the first bus system and the third bus system via the peripheral port and bridging circuit, enabling an exchange of information to take place.

Claim 24

The method of claim 19 wherein said changing step comprises the step of writing data and address information into the memory storage device without physically removing the storage device from the computer system.

Claim 25

The method of claim 19 further including the steps of: asserting a BUSY signal to the CPU during at least a portion of time when the bridging circuit is being reconfigured to prevent access to said bridging circuit, and asserting a READY signal to the CPU during at least a portion of time when the bridging circuit is not being reconfigured to allow access to said bridging circuit.

Claim 26

The method of claim 17 wherein said configuring step (b) includes the step of configuring the bridging circuit to bridge a communication path between a PCMCIA bus system and the second bus system without removing the bridging circuit from the computer system.

Claim 27

The method of claim 17 wherein said configuring step (b) includes the step of hotly configuring the bridging circuit, using the stored configuration programming information, without requiring that the computer system be rebooted.

Claim 28

In a computer system comprising a CPU, a first parallel bus system, at least one peripheral port, and a reconfigurable bridging circuit connected to the peripheral port for bridging a communication path between the first parallel bus system and a plurality of other parallel bus systems not directly compatible with the first bus system, said computer system further comprising a memory storage device for storing configuration programming information used to configure the bridging circuit to bridge the first bus system with at least one of the plurality of other bus systems, a method for reconfiguring the bridging circuit to bridge a communication path between the first bus system and one of the plurality of other bus systems, said method comprising the steps of: hotly writing configuration programming information into the memory storage device, while the computer system is operating, without physically removing the storage device from the computer system; reading the rewritten configuration programming information from the memory storage device; and using the configuration programming information read from the memory storage device to hotly reconfigure the bridging circuit, while the computer system is operating to bridge a communication path between the first bus system and one of the plurality of other bus systems, wherein the one of the other plurality of parallel bus systems is of a different type than another of the other plurality of parallel bus systems.

Claim 29

In a computer system comprising a CPU, a first parallel bus system, at least one peripheral port, and a reconfigurable bridging circuit connected to the peripheral port for bridging a communication path between the first parallel bus system and a plurality of other parallel bus systems not directly compatible with the first bus system, said computer system further comprising a memory storage device for storing configuration programming information used to configure the bridging circuit to bridge the first bus system with at least one of the plurality of other bus systems, a method for reconfiguring the bridging circuit to bridge a communication path between the first bus system and one of the plurality of other bus systems, said method comprising the steps of: hotly writing configuration programming information into the memory storage device, while the computer system is operating, without physically removing the storage device from the computer system; reading the rewritten configuration programming information from the memory storage device; and using the configuration programming information read from the memory storage device to hotly reconfigure the bridging circuit, while the computer system is operating to bridge a communication path between the first bus system and one of the plurality of other bus systems, wherein the one of the other plurality of parallel bus systems is of a different type than another of the other plurality of parallel bus systems.

Claim 30

The method of claim 24 wherein said using step includes the step of using the configuration programming information read from the memory storage device to reconfigure the bridging circuit to bridge a communication path between the first bus system and one of the plurality of other bus systems, without requiring that the computer system be rebooted.

Claim 31

For use in a computer system having a CPU, a first parallel bus, and a receptacle for connecting said system to a plurality of other parallel busses, wherein a communication protocol of the first bus is not directly compatible with a communication protocol of at least one of the other busses, an insertable, reprogrammable adaptor circuit connectable to said receptacle and said other parallel busses for transparently interfacing the first bus with any one of the plurality of other busses, said adaptor circuit comprising: a hot reprogrammable bridging circuit responsive to configuration programming information for interfacing the first bus with any one of the other busses, wherein said bridging circuit includes means for performing protocol conversion between said first bus and said one other bus; a memory storage device located on said adaptor circuit for storing said configuration programming information used to configure said bridging circuit; programming means located on said adaptor circuit for applying said configuration programming information to configure said bridging circuit to interface the first bus with said one other bus; and bus identification means located on said adaptor circuit and in communication with said programming means for automatically identifying the communication protocol of said first bus, and for automatically causing said programming means to use at least a first portion of said configuration programming information to configure said bridging circuit to communicate with said first bus using said first bus communication protocol; said bus identification means further including secondary means responsive to a request from said first bus to communicate with one of the plurality of other busses for automatically identifying the communication protocol of said other bus; and for automatically causing said programming means to use at least a second portion of said configuration programming information to configure said bridging circuit to communicate with said other bus using the communication protocol of said other bus, wherein said bridging circuit is thereby configured to interface said first bus with said other bus, wherein the one of the other plurality of parallel bus systems is of a different type than another of the other plurality of parallel bus systems.

Claim 32

For use in a computer system having a CPU, a first parallel bus, and a receptacle for connecting said system to a plurality of other parallel busses, wherein a communication protocol of the first bus is not directly compatible with a communication protocol of at least one of the other busses, an insertable, reprogrammable adaptor circuit connectable to said receptacle and said other parallel busses for transparently interfacing the first bus with any one of the plurality of other busses, said adaptor circuit comprising: a hot reprogrammable bridging circuit responsive to configuration programming information for interfacing the first bus with any one of the other busses, wherein said bridging circuit includes means for performing protocol conversion between said first bus and said one other bus; a memory storage device located on said adaptor circuit for storing said configuration programming information used to configure said bridging circuit; programming means located on said adaptor circuit for applying said configuration programming information to configure said bridging circuit to interface the first bus with said one other bus; and bus identification means located on said adaptor circuit and in communication with said programming means for automatically identifying the communication protocol of said first bus, and for automatically causing said programming means to use at least a first portion of said configuration programming information to configure said bridging circuit to communicate with said first bus using said first bus communication protocol; said bus identification means further including secondary means responsive to a request from said first bus to communicate with one of the plurality of other busses for automatically identifying the communication protocol of said other bus; and for automatically causing said programming means to use at least a second portion of said configuration programming information to configure said bridging circuit to communicate with said other bus using the communication protocol of said other bus, wherein said bridging circuit is thereby configured to interface said first bus with said other bus, wherein the one of the other plurality of parallel bus systems is of a different type than another of the other plurality of parallel bus systems.

Claim 33

The adaptor circuit of claim 26 wherein said secondary means is further responsive to a request from said first bus to communicate with a different one of the plurality of other busses for automatically identifying the communication protocol of said different bus; and for automatically causing said programming means to use at least a third portion of said configuration programming information to hot reconfigure said bridging circuit to interface said first bus with said different bus without causing a bus error or system error.

Claim 34

The circuit of claim 27 wherein said secondary means further causes said bridging circuit to be hot reconfigured to interface said first bus with said different bus without resetting or rebooting the computer system.

Claim 35

The circuit of claim 27 wherein said bridging circuit, said memory storage device, said programming means, said bus identification means and said secondary means cooperate together to cause said bridging circuit to be hot reconfigured to interface said first bus with said different bus without utilizing the CPU to reconfigure the bridging circuit.

Claim 36

The circuit of claim 27 wherein said memory storage device comprises an EEPROM.

Claim 37

The circuit of claim 27 wherein said memory storage device comprises a slave microprocessor and memory storage componentry.

Claim 38

The adaptor circuit of claim 26 wherein said bridging circuit further comprises: means for performing buffering between said first bus and said other bus; and means for performing speed matching of information communicated between said first bus and said other bus.

Claim 39

The circuit of claim 26 wherein said programming means comprises means for preventing access to said bridging circuit while said bridging circuit is being configured by said programming means, and for allowing access to said bridging circuit after said bridging circuit has been configured.

Claim 40

For use in a computer system having a CPU, a first parallel bus, and a receptacle for connecting said system to a plurality of other parallel busses, wherein a communication protocol of the first bus is not directly compatible with a communication protocol of at least one of the other busses, a reprogrammable adaptor circuit connectable to said receptacle and said other parallel busses for interfacing the first bus with any one of the plurality of other busses, said adaptor circuit comprising: a hot reprogrammable bridging circuit responsive to configuration programming information for interfacing the first bus with any one of the other busses, wherein said bridging circuit includes means for performing protocol conversion between said first bus and said one other bus; a memory storage device in communication with said CPU for storing said configuration programming information used to configure said bridging circuit; programming means in communication with said CPU for applying said configuration programming information to configure said bridging circuit to interface the first bus with said one other bus; bus identification means in communication with said programming means for causing said programming means to use at least a first portion of said configuration programming information to configure said bridging circuit to communicate with said first bus using said first bus communication protocol, and for causing said programming means to use at least a second portion of said configuration programming information to configure said bridging circuit to communicate with said other bus using the communication protocol of said other bus; and means in communication with the CPU for changing at least a portion of the configuration programming information stored within said memory storage device while the system is in operation, without causing a system or bus error, and without physically removing the storage device or the bridging circuit from the adaptor circuit; wherein said secondary means is further responsive to a request from said first bus to communicate with a different one of the plurality of other busses for causing said programming means to use said changed configuration programming information to hot reconfigure said bridging circuit to interface said first bus with said different bus, wherein the one of the other plurality of parallel bus systems is of a different type than the different one of the other plurality of parallel bus systems.

Claim 41

For use in a computer system having a CPU, a first parallel bus, and a receptacle for connecting said system to a plurality of other parallel busses, wherein a communication protocol of the first bus is not directly compatible with a communication protocol of at least one of the other busses, a reprogrammable adaptor circuit connectable to said receptacle and said other parallel busses for interfacing the first bus with any one of the plurality of other busses, said adaptor circuit comprising: a hot reprogrammable bridging circuit responsive to configuration programming information for interfacing the first bus with any one of the other busses, wherein said bridging circuit includes means for performing protocol conversion between said first bus and said one other bus; a memory storage device in communication with said CPU for storing said configuration programming information used to configure said bridging circuit; programming means in communication with said CPU for applying said configuration programming information to configure said bridging circuit to interface the first bus with said one other bus; bus identification means in communication with said programming means for causing said programming means to use at least a first portion of said configuration programming information to configure said bridging circuit to communicate with said first bus using said first bus communication protocol, and for causing said programming means to use at least a second portion of said configuration programming information to configure said bridging circuit to communicate with said other bus using the communication protocol of said other bus; and means in communication with the CPU for changing at least a portion of the configuration programming information stored within said memory storage device while the system is in operation, without causing a system or bus error, and without physically removing the storage device or the bridging circuit from the adaptor circuit; wherein said secondary means is further responsive to a request from said first bus to communicate with a different one of the plurality of other busses for causing said programming means to use said changed configuration programming information to hot reconfigure said bridging circuit to interface said first bus with said different bus, wherein the one of the other plurality of parallel bus systems is of a different type than the different one of the other plurality of parallel bus systems.

Claim 42

The system of claim 34 wherein said adaptor circuit further comprises: means for performing buffering between said first bus and said second bus; and means for performing speed matching of information communicated between said first bus and said second bus.

Claim 43

The circuit of claim 34 wherein, said programming means comprises means for preventing access to said adaptor circuit while said adaptor circuit is being reconfigured by said reconfiguring means, and for allowing access to said adaptor circuit after said adaptor circuit has been reconfigured; and wherein said changing means comprises a plurality of registers for intermediately latching new configuration information related to the reconfiguring of said adaptor circuit to facilitate the hot reconfiguration of said adaptor circuit without causing a system or bus error.

Claim 44

The circuit of claim 34 wherein said memory storage device comprises an EEPROM.

Claim 45

The circuit of claim 34 wherein said memory storage device comprises a slave microprocessor and memory storage componentry.

Claim 46

In a computer system comprising a CPU, a first parallel bus, at least one receptacle, and a hot reconfigurable bridging circuit connected to the receptacle for bridging a communication path between the first parallel bus and a plurality of other parallel buses which are not directly compatible with the first bus, a method for transparently communicating between the first bus and at least one of the plurality of other buses via the receptacle and bridging circuit, said method comprising the steps of: (a) identifying a communication protocol of said first bus; (b) using a first portion of configuration programming information to configure said bridging circuit to communicate with said first bus using said first bus communication protocol; (c) upon receiving a request from said first bus to communicate with one of the plurality of other busses, identifying a communication protocol of said other bus; (d) using a second portion of said configuration programming information to configure said bridging circuit to communicate with said other bus using the communication protocol of said other bus, wherein said bridging circuit is thereby configured to interface said first bus with said other bus; and (e) upon receiving a request from said first bus to communicate with a different one of the plurality of other busses, identifying a communication protocol of said different bus, and using a third portion of said configuration programming information to hot reconfigure said bridging circuit to interface said first bus with said different bus without causing a bus error or system error, wherein the one of the other plurality of parallel bus systems is of a different type than the different one of the other plurality of parallel bus systems.

Claim 47

In a computer system comprising a CPU, a first parallel bus, at least one receptacle, and a hot reconfigurable bridging circuit connected to the receptacle for bridging a communication path between the first parallel bus and a plurality of other parallel buses which are not directly compatible with the first bus, a method for transparently communicating between the first bus and at least one of the plurality of other buses via the receptacle and bridging circuit, said method comprising the steps of: (a) identifying a communication protocol of said first bus; (b) using a first portion of configuration programming information to configure said bridging circuit to communicate with said first bus using said first bus communication protocol; (c) upon receiving a request from said first bus to communicate with one of the plurality of other busses, identifying a communication protocol of said other bus; (d) using a second portion of said configuration programming information to configure said bridging circuit to communicate with said other bus using the communication protocol of said other bus, wherein said bridging circuit is thereby configured to interface said first bus with said other bus; and (e) upon receiving a request from said first bus to communicate with a different one of the plurality of other busses, identifying a communication protocol of said different bus, and using a third portion of said configuration programming information to hot reconfigure said bridging circuit to interface said first bus with said different bus without causing a bus error or system error, wherein the one of the other plurality of parallel bus systems is of a different type than the different one of the other plurality of parallel bus systems.

Claim 48

The method of claim 39 further including the steps of: using the bridging circuit to perform protocol conversion between the first bus and said other bus; and using the reconfigured bridging circuit to perform protocol conversion between the first bus and the different bus.

Claim 50

The method of claim 39 wherein said reconfiguration step (e) includes the step of reconfiguring said bridging circuit to interface said first bus with said different bus without resetting or rebooting the computer system.

Claim 51

The method of claim 39 further including the steps of: asserting a BUSY signal during at least a portion of time while the bridging circuit is being reconfigured to prevent access to said bridging circuit, and asserting a READY signal during at least a portion of time while the bridging circuit is not being reconfigured to allow access to said bridging circuit.

Claim 52

The method of claim 39 wherein said reconfiguration step (e) includes the step of reconfiguring said bridging circuit, using at least a portion of the rewritten configuration programming information, to interface said first bus with said different bus without utilizing the CPU to reconfigure the bridging circuit.

Claim 53

In a computer system comprising a CPU, a first parallel bus, at least one receptacle, and a reconfigurable bridging circuit connected to the receptacle for interfacing the first parallel bus with a plurality of other parallel buses not directly compatible with the first bus, said computer system further comprising a memory storage device located on the bridging circuit for storing configuration programming information used to configure the bridging circuit to interface the first bus with at least one of the plurality of other buses, a method for interfacing the first bus with one of the plurality of other buses via the receptacle and bridging circuit, said method comprising the steps of: (a) using at least a first portion of the configuration programming information to configure said bridging circuit to communicate with said first bus using a communication protocol of the first bus; (b) using at least a second portion of said configuration programming information to configure said bridging circuit to communicate with said other bus using a communication protocol of said other bus; (c) using the CPU to change at least a portion of the configuration programming information stored within the memory storage device while the system is in operation, without causing a system or bus error, and without physically removing the storage device or the bridging circuit from the adaptor circuit; and (d) using said changed configuration programming information to hot reconfigure said bridging circuit to interface said first bus with said different bus while the system is in operation, without causing a system or bus error, wherein said step (d) includes the step of using at least a second portion of said changed configuration programming information to reconfigure said bridging circuit to communicate with said different bus using a communication protocol of said different bus, wherein the one of the other plurality of parallel bus systems is of a different type than the different one of the other plurality of parallel bus systems.

Claim 54

In a computer system comprising a CPU, a first parallel bus, at least one receptacle, and a reconfigurable bridging circuit connected to the receptacle for interfacing the first parallel bus with a plurality of other parallel buses not directly compatible with the first bus, said computer system further comprising a memory storage device located on the bridging circuit for storing configuration programming information used to configure the bridging circuit to interface the first bus with at least one of the plurality of other buses, a method for interfacing the first bus with one of the plurality of other buses via the receptacle and bridging circuit, said method comprising the steps of: (a) using at least a first portion of the configuration programming information to configure said bridging circuit to communicate with said first bus using a communication protocol of the first bus; (b) using at least a second portion of said configuration programming information to configure said bridging circuit to communicate with said other bus using a communication protocol of said other bus; (c) using the CPU to change at least a portion of the configuration programming information stored within the memory storage device while the system is in operation, without causing a system or bus error, and without physically removing the storage device or the bridging circuit from the adaptor circuit; and (d) using said changed configuration programming information to hot reconfigure said bridging circuit to interface said first bus with said different bus while the system is in operation, without causing a system or bus error, wherein said step (d) includes the step of using at least a second portion of said changed configuration programming information to reconfigure said bridging circuit to communicate with said different bus using a communication protocol of said different bus, wherein the one of the other plurality of parallel bus systems is of a different type than the different one of the other plurality of parallel bus systems.

Claim 55

The method of claim 45 further including the steps of: using the bridging circuit to perform protocol conversion between the first bus and said other bus; and using the reconfigured bridging circuit to perform protocol conversion between the first bus and the different bus.

Claim 56

The method of claim 46 further including the steps of: using the bridging circuit to perform buffering between the first bus and the other bus; using the bridging circuit to perform speed matching of information communicated between the first bus and the other bus; using the reconfigured bridging circuit to perform buffering between the first bus and the different bus; and using the reconfigured bridging circuit to perform speed matching of information communicated between the first bus and the different bus.

Claim 57

The method of claim 45 wherein said reconfiguration step (d) includes the step of reconfiguring said bridging circuit to interface said first bus with said different bus without resetting or rebooting the computer system.

Claim 58

The method of claim 45 further including the steps of: asserting a BUSY signal during at least a portion of time while the bridging circuit is being reconfigured to prevent access to said bridging circuit; asserting a READY signal during at least a portion of time while the bridging circuit is not being reconfigured to allow access to said bridging circuit; and latching new configuration information related to the reconfiguration of said bridging circuit to facilitate the hot reconfiguration of said adaptor circuit without causing a system or bus error.

Claim 59

For use in a computer system having a CPU and a parallel PCMCIA bus system, a reprogrammable adaptor circuit for bridging the PCMCIA parallel bus system to a non-PCMCIA parallel bus system: a bridging circuit responsive to configuration programming information for bridging a communication path between the parallel PCMCIA bus system and non-PCMCIA parallel bus; a memory storage device for storing said configuration programming information used to configure said bridging circuit; programming means for applying said configuration programming information to configure said bridging circuit to establish said bridged communication path; and means in communication with the CPU for changing the configuration programming information stored within said memory storage device while the computer system is operating, without physically removing the storage device or the bridging circuit from the adaptor circuit, thereby hotly reconfiguring said bridging circuit, wherein the changed configuration information allows the bridging circuit to bridge a communication path between the non-PCMCIA parallel bus system and an additional parallel bus system.

Claim 60

For use in a computer system having a CPU and a parallel PCMCIA bus system, a reprogrammable adaptor circuit for bridging the PCMCIA parallel bus system to a non-PCMCIA parallel bus system: a bridging circuit responsive to configuration programming information for bridging a communication path between the parallel PCMCIA bus system and non-PCMCIA parallel bus; a memory storage device for storing said configuration programming information used to configure said bridging circuit; programming means for applying said configuration programming information to configure said bridging circuit to establish said bridged communication path; and means in communication with the CPU for changing the configuration programming information stored within said memory storage device while the computer system is operating, without physically removing the storage device or the bridging circuit from the adaptor circuit, thereby hotly reconfiguring said bridging circuit, wherein the changed configuration information allows the bridging circuit to bridge a communication path between the non-PCMCIA parallel bus system and an additional parallel bus system.