US5802572A
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Write-back cache having sub-line size coherency granularity and method for maintaining coherency within a write-back cache
Assignee: International Business Machines Corp
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Filing: 1996-03-15
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Granted: 1998-09-01
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Expires: 2016-03-15
Abstract
Abstract A write-back cache memory and method for maintaining coherency within a write-back cache memory are disclosed. The write-back cache memory includes a number of cache lines for storing data associated with addresses within an associated memory. Each of the cache lines comprises multiple byte sets. The write-back cache memory also includes coherency indicia for identifying each byte set among the multiple byte sets within a cache line which contains data that differs from data stored in corresponding addresses within the associated memory. The write-back cache memory further includes cache control logic, which, upon replacement of a particular cache line within the write-back cache memory, writes only identified byte sets to the associated memory, such that memory accesses and bus utilization are minimized.
Inventors
- 👤 Rajesh Bhikhubhai Patel
- 👤 Soummya Mallick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:18
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0804
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
140 words
A cache memory, comprising: a plurality of cache lines for storing data associated with addresses within an associated memory, each of said plurality of cache lines containing a plurality of byte sets, wherein write accesses to said plurality of cache lines can be configured as write-through or write-back on a per cache line basis; coherency indicia for identifying each byte set among said plurality of byte sets within a cache line that contains data that differs from data stored in corresponding addresses within said associated memory, said coherency indicia being set to identify a byte set within a particular cache line among said plurality of cache lines only in response to a write-back access to said particular cache line; and cache control logic that upon replacement of said particular cache line writes only identified byte sets to said associated memory.
Claim 2
Dependent Claim
140 words
A cache memory, comprising: a plurality of cache lines for storing data associated with addresses within an associated memory, each of said plurality of cache lines containing a plurality of byte sets, wherein write accesses to said plurality of cache lines can be configured as write-through or write-back on a per cache line basis; coherency indicia for identifying each byte set among said plurality of byte sets within a cache line that contains data that differs from data stored in corresponding addresses within said associated memory, said coherency indicia being set to identify a byte set within a particular cache line among said plurality of cache lines only in response to a write-back access to said particular cache line; and cache control logic that upon replacement of said particular cache line writes only identified byte sets to said associated memory.
Claim 3
Dependent Claim
32 words
The cache memory of claim 1, wherein said coherency indicia comprise a plurality of bits, wherein each of said plurality of bits is associated with one of said plurality of byte sets.
Claim 4
Dependent Claim
31 words
The cache memory of claim 1, wherein each of said byte sets includes a maximum number of bytes that can be simultaneously written to said associated memory by said cache memory.
Claim 5
Dependent Claim
52 words
The cache memory of claim 1, each of said plurality of cache lines having a plurality of ways that each contain a plurality of byte sets, wherein each of said plurality of ways has coherency indicia for identifying each modified byte set among said plurality of byte sets within said each way.
Claim 6
Dependent Claim
19 words
The cache memory of claim 1, wherein said cache memory comprises an upper level cache associated with a processor.
Claim 7
Dependent Claim
24 words
The cache memory of claim 1, wherein said cache control logic replaces said particular cache line according to a least recently used (LRU) algorithm.
Claim 8
Dependent Claim
15 words
The cache memory of claim 1, wherein said cache memory is a lower level cache.
Claim 9
Dependent Claim
169 words
A data processing system, comprising: a processor; an associated memory coupled to said processor; a cache memory coupled to said associated memory, said cache memory including: a plurality of cache lines for storing data associated with addresses within said memory, each of said plurality of cache lines containing a plurality of byte sets, wherein write accesses to said plurality of cache lines can be configured as write-through or write-back on a per cache line basis; coherency indicia for identifying each byte set among said plurality of byte sets within a cache line that contains data that differs from data stored in corresponding addresses within said associated memory, said coherency indicia being set to identify a byte set within a particular cache line among said plurality of cache lines only in response to a write-back access to said particular cache line; and cache control logic, wherein upon replacement of a particular cache line within said cache memory, said cache control logic writes only identified byte sets to said associated memory.
Claim 10
Dependent Claim
169 words
A data processing system, comprising: a processor; an associated memory coupled to said processor; a cache memory coupled to said associated memory, said cache memory including: a plurality of cache lines for storing data associated with addresses within said memory, each of said plurality of cache lines containing a plurality of byte sets, wherein write accesses to said plurality of cache lines can be configured as write-through or write-back on a per cache line basis; coherency indicia for identifying each byte set among said plurality of byte sets within a cache line that contains data that differs from data stored in corresponding addresses within said associated memory, said coherency indicia being set to identify a byte set within a particular cache line among said plurality of cache lines only in response to a write-back access to said particular cache line; and cache control logic, wherein upon replacement of a particular cache line within said cache memory, said cache control logic writes only identified byte sets to said associated memory.
Claim 11
Dependent Claim
33 words
The data processing system of claim 8, wherein said coherency indicia comprise a plurality of bits, wherein each of said plurality of bits is associated with one of said plurality of byte sets.
Claim 12
Dependent Claim
32 words
The data processing system of claim 8, wherein each of said byte sets includes a maximum number of bytes that can be simultaneously written to said associated memory by said cache memory.
Claim 13
Dependent Claim
53 words
The data processing system of claim 8, each of said plurality of cache lines having a plurality of ways that each contain a plurality of byte sets, wherein each of said plurality of ways has coherency indicia for identifying each modified byte set among said plurality of byte sets within said each way.
Claim 14
Dependent Claim
16 words
The data processing system of claim 8, wherein said cache memory comprises an upper level cache.
Claim 15
Dependent Claim
25 words
The data processing system of claim 8, wherein said cache control logic replaces said particular cache line according to a least recently used (LRU) algorithm.
Claim 16
Dependent Claim
31 words
The data processing system of claim 8, wherein said cache memory is a lower level cache and said data processing system further comprises an upper level cache associated with said processor.
Claim 17
Independent Claim
128 words
A method for maintaining coherency within a cache memory having a plurality of cache lines, said method comprising: configuring each write access to data stored within said plurality of cache lines as write-through or write-back on a per cache line basis; storing data within a particular cache line among said plurality of cache lines, wherein said data stored within said particular cache line is associated with addresses within an associated memory; only for write-back accesses, identifying each byte set among a plurality of byte sets within said particular cache line which contains data that differs from data stored in corresponding addresses within said associated memory; and in response to replacement of said particular cache line within said cache memory, writing only identified byte sets to said associated memory.
Claim 18
Independent Claim
128 words
A method for maintaining coherency within a cache memory having a plurality of cache lines, said method comprising: configuring each write access to data stored within said plurality of cache lines as write-through or write-back on a per cache line basis; storing data within a particular cache line among said plurality of cache lines, wherein said data stored within said particular cache line is associated with addresses within an associated memory; only for write-back accesses, identifying each byte set among a plurality of byte sets within said particular cache line which contains data that differs from data stored in corresponding addresses within said associated memory; and in response to replacement of said particular cache line within said cache memory, writing only identified byte sets to said associated memory.
Claim 19
Dependent Claim
43 words
The method for maintaining coherency within a cache memory of claim 15, said cache memory having a plurality of bits associated therewith, wherein said identifying step comprises setting a bit among said plurality of bits associated with each byte set to be identified.
Claim 20
Dependent Claim
45 words
The method for maintaining coherency within a cache memory of claim 15, said cache memory and said associated memory being coupled by a bus, wherein said writing step comprises simultaneously writing all bytes in an identified byte set to said associated memory via said bus.
Claim 21
Dependent Claim
89 words
The, method for maintaining coherency within a cache memory of claim 15, each of said plurality of cache lines having a plurality of ways that each contain a plurality of byte sets, wherein each of said plurality of ways has coherency indicia for identifying each modified byte set among said plurality of byte sets within each way, and wherein said identifying step comprises setting a bit associated with a byte set to be identified among a plurality of byte sets within a selected way of said particular cache line.
Claim 22
Dependent Claim
27 words
The method for maintaining coherency within a cache memory of claim 15, wherein said particular cache line is replaced according to a least recently used (LRU) algorithm.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-08-31 | 2002-03-02 | 2002-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-31 | 2006-03-02 | 2006-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-31 | 2010-03-02 | 2010-09-01 | $7700.00 | Window Closed / Lapsed |