Method for deciding the feasibility of logic circuit prior to performing logic synthesis

Claim 1

A method for designing a logic circuit by using hardware description language (HDL), said logic circuit comprising sequential circuits and combinational circuits, said method comprising steps of: producing an HDL description of said logic circuit; performing a feasibility decision by using said HDL description, said feasibility decision comprising: a first decision for determining whether at least one of a clock signal and a reset signal of any of said sequential circuits is output from any of said combinational circuits; and a second decision for determining whether an output signal of any of said combinational circuits is recursively input thereto without passing through one of said sequential circuits; and performing logic synthesis for said HDL description which passes said feasibility decision; wherein said feasibility decision further comprises the steps of: identifying description units in said HDL description, each of said description units comprising a startup condition description starting with changes of a variable representative of a signal and a procedure description comprising a condition decision statement and an assignment statement; identifying each of said description units as one of a sequential circuit description unit and a combinational circuit description unit; and identifying connection relationships of said description units based on input signals and output signals of said description units.

Claim 2

A method for designing a logic circuit by using hardware description language (HDL), said logic circuit comprising sequential circuits and combinational circuits, said method comprising steps of: producing an HDL description of said logic circuit; performing a feasibility decision by using said HDL description, said feasibility decision comprising: a first decision for determining whether at least one of a clock signal and a reset signal of any of said sequential circuits is output from any of said combinational circuits; and a second decision for determining whether an output signal of any of said combinational circuits is recursively input thereto without passing through one of said sequential circuits; and performing logic synthesis for said HDL description which passes said feasibility decision; wherein said feasibility decision further comprises the steps of: identifying description units in said HDL description, each of said description units comprising a startup condition description starting with changes of a variable representative of a signal and a procedure description comprising a condition decision statement and an assignment statement; identifying each of said description units as one of a sequential circuit description unit and a combinational circuit description unit; and identifying connection relationships of said description units based on input signals and output signals of said description units.

Claim 5

A method for designing a logic circuit by using hardware description language (HDL), said logic circuit comprising sequential circuits and combinational circuits, said method comprising steps of: producing an HDL description of said logic circuit; performing a feasibility decision by using said HDL description, said feasibility decision comprising: a first decision for determining whether at least one of a clock signal and a reset signal of any of said sequential circuits is output from any of said combinational circuits; and a second decision for determining whether an output signal of any of said combinational circuits is recursively input thereto without passing through one of said sequential circuits; and performing logic synthesis for said HDL description which passes said feasibility decision; wherein said feasibility decision further comprises the steps of: calculating an output delay time of said logic circuit by using a predetermined delay estimation formula representing a relationship between a delay time of a statement including at least a variable and the number of bits of said at least a variable; calculating a circuit scale of said logic circuit by using a predetermined circuit scale estimation formula representing a relationship between types of the statement and the number of logic gates; and calculating power consumption for said logic circuit based on said circuit scale.

Claim 6

A method for designing a logic circuit by using hardware description language (HDL), said logic circuit comprising sequential circuits and combinational circuits, said method comprising steps of: producing an HDL description of said logic circuit; performing a feasibility decision by using said HDL description, said feasibility decision comprising: a first decision for determining whether at least one of a clock signal and a reset signal of any of said sequential circuits is output from any of said combinational circuits; and a second decision for determining whether an output signal of any of said combinational circuits is recursively input thereto without passing through one of said sequential circuits; and performing logic synthesis for said HDL description which passes said feasibility decision; wherein said feasibility decision further comprises the steps of: calculating an output delay time of said logic circuit by using a predetermined delay estimation formula representing a relationship between a delay time of a statement including at least a variable and the number of bits of said at least a variable; calculating a circuit scale of said logic circuit by using a predetermined circuit scale estimation formula representing a relationship between types of the statement and the number of logic gates; and calculating power consumption for said logic circuit based on said circuit scale.

Claim 9

A method for determining feasibility of a logic circuit by using hardware description language (HDL), said logic circuit comprising sequential circuits and combinational circuits, said method comprising the steps of: a) producing an HDL description of said logic circuit; b) performing a spike check and an oscillation check of the HDL description; c) determining the feasibility of the logic circuit depending on whether the HDL description passes both the spike check and the oscillation check; and d) repeating the steps a) to c) by changing the HDL description until the HDL description passes both the spike check and the oscillation check; wherein in the step b): the spike check checks whether at least one of a clock signal and a reset signal of any of said sequential circuits is output from any of said combinational circuits; and the oscillation check checks whether an output signal of any of said combinational circuits is recursively input thereto without passing through one of said sequential circuits; wherein the step b) further comprises the steps of: identifying description units in said HDL description, each of said description units comprising a startup condition description starting with a change of a variable representative of a signal and a procedure description comprising a condition decision statement and an assignment statement; identifying each of said description units as one of a sequential circuit description unit and a combinational circuit description unit; and identifying connection relationships of said description units based on input signals and output signals of said description units.

Claim 10

A method for determining feasibility of a logic circuit by using hardware description language (HDL), said logic circuit comprising sequential circuits and combinational circuits, said method comprising the steps of: a) producing an HDL description of said logic circuit; b) performing a spike check and an oscillation check of the HDL description; c) determining the feasibility of the logic circuit depending on whether the HDL description passes both the spike check and the oscillation check; and d) repeating the steps a) to c) by changing the HDL description until the HDL description passes both the spike check and the oscillation check; wherein in the step b): the spike check checks whether at least one of a clock signal and a reset signal of any of said sequential circuits is output from any of said combinational circuits; and the oscillation check checks whether an output signal of any of said combinational circuits is recursively input thereto without passing through one of said sequential circuits; wherein the step b) further comprises the steps of: identifying description units in said HDL description, each of said description units comprising a startup condition description starting with a change of a variable representative of a signal and a procedure description comprising a condition decision statement and an assignment statement; identifying each of said description units as one of a sequential circuit description unit and a combinational circuit description unit; and identifying connection relationships of said description units based on input signals and output signals of said description units.

Claim 13

A method for determining feasibility of a logic circuit by using hardware description language (HDL), said logic circuit comprising sequential circuits and combinational circuits, said method comprising the steps of: a) producing an HDL description of said logic circuit: b) performing a spike check and an oscillation check of the HDL description: c) determining the feasibility of the logic circuit depending on whether the HDL description passes both the spike check and the oscillation check; and d) repeating the steps a) to c) by changing the HDL description until the HDL description passes both the spike check and the oscillation check; wherein said step c) further comprises the steps of: calculating an output delay time of said logic circuit by using a predetermined delay estimation formula representing a relationship between a delay time of a statement including at least one variable and the number of bits of said at least one variable; calculating a circuit scale of said logic circuit by using a predetermined circuit scale estimation formula representing a relationship between types of the statement and the number of logic gates; and calculating power consumption for said logic circuit based on said circuit scale.

Claim 14

A method for determining feasibility of a logic circuit by using hardware description language (HDL), said logic circuit comprising sequential circuits and combinational circuits, said method comprising the steps of: a) producing an HDL description of said logic circuit: b) performing a spike check and an oscillation check of the HDL description: c) determining the feasibility of the logic circuit depending on whether the HDL description passes both the spike check and the oscillation check; and d) repeating the steps a) to c) by changing the HDL description until the HDL description passes both the spike check and the oscillation check; wherein said step c) further comprises the steps of: calculating an output delay time of said logic circuit by using a predetermined delay estimation formula representing a relationship between a delay time of a statement including at least one variable and the number of bits of said at least one variable; calculating a circuit scale of said logic circuit by using a predetermined circuit scale estimation formula representing a relationship between types of the statement and the number of logic gates; and calculating power consumption for said logic circuit based on said circuit scale.