Embedded memory for field programmable gate array

Claim 2

A programmable logic device, comprising: a plurality of input/output cells; a configurable logic array of configurable logic cells and interconnect structures; a memory array of memory elements coupled with the configurable logic array such that memory elements in the memory array store data to program the configurable logic array, said memory array including a subarray of addressable memory elements coupled with a corresponding subarray of the configurable logic array; memory access logic coupled with the memory array and the plurality of input/output cells, the memory access logic including address decode logic configurable to receive address signals from the plurality of input/output cells and memory data path logic configurable to receive data signals from and supply data signals to the plurality of input/output cells; a subarray decoder coupled to the configurable logic array, the subarray decoder coupled to said subarray of the memory array and decoding address signals from the interconnect structures of the configurable logic array to address memory elements in said subarray; and a subarray I/O path coupled to the configurable logic array, the subarray I/O path coupled to said subarray of the memory array and providing input and output data signals between the interconnect structures of the configurable logic array and addressed memory elements in said subarray.

Claim 3

The programmable logic device of claim 1, wherein the memory array includes a second subarray of addressable memory elements, and including a second subarray decoder coupled to the configurable logic array, the second subarray decoder coupled to said second subarray of the memory array and decoding address signals from the interconnect structures of the configurable logic array to address memory elements in said second subarray; and a second subarray I/O path coupled to the interconnect structure of the configurable logic array, the second subarray I/O path coupled to said second subarray of the memory array and providing input and output data signals between the interconnect structures of the configurable logic array and addressed memory elements in said second subarray.

Claim 4

The programmable logic device of claim 1, including: a programmable interconnect circuit connected to the configurable logic array and to said subarray of the memory array, the programmable interconnect circuit including inputs connected to the configurable logic array, and inputs connected to the data I/O path for said subarray of the memory array, and including outputs connected to the configurable logic array, outputs connected to said data I/O path for said subarray of the memory array, and outputs connected to the subarray decoder for said subarray of the memory array.

Claim 5

The programmable logic device of claim 1, wherein the configurable logic cells comprise programmable elements configurable in response to data in the memory array to provide a storage element and a logic function.

Claim 6

The programmable logic device of claim 1, wherein the memory array comprises an array of static random access memory cells.

Claim 7

The programmable logic device of claim 1, wherein the subarray of the configurable logic array to which said subarray of the memory array corresponds, includes 256 or fewer configurable logic cells.

Claim 8

A programmable logic device, comprising: a plurality of input/output cells; a configurable logic array of configurable logic cells and interconnect structures; a memory array of memory elements, coupled with the configurable logic array, such that memory elements in the memory array store data to program the configurable logic array, said memory array including a set, having more than one member, of subarrays of addressable memory elements, members of said set coupled with corresponding subarrays of the configurable logic array; memory access logic coupled with the memory array and the plurality of input/output cells, the memory access logic including address decode logic configurable to receive address signals from the plurality of input/output cells, and memory data path logic configurable to receive data signals from and supply data signals to the plurality of input/output cells; a plurality of subarray decoders and corresponding configurable interconnect circuits coupled to the configurable logic array, the subarray decoders programmably connectable by the corresponding configurable interconnect circuits to corresponding subarrays in said set of subarrays and decoding address signals from the interconnect structures of the configurable logic array to address memory elements in corresponding subarrays; and a plurality of subarray I/O path circuits and corresponding configurable interconnect circuits coupled to the configurable logic array, the subarray I/O path circuits programmably connectable by the corresponding configurable interconnect circuits to corresponding subarrays of said set of subarrays and providing input and output data signals between the interconnect structures of the configurable logic array and addressed memory elements in corresponding subarrays.

Claim 9

A programmable logic device, comprising: a plurality of input/output cells; a configurable logic array of configurable logic cells and interconnect structures; a memory array of memory elements, coupled with the configurable logic array, such that memory elements in the memory array store data to program the configurable logic array, said memory array including a set, having more than one member, of subarrays of addressable memory elements, members of said set coupled with corresponding subarrays of the configurable logic array; memory access logic coupled with the memory array and the plurality of input/output cells, the memory access logic including address decode logic configurable to receive address signals from the plurality of input/output cells, and memory data path logic configurable to receive data signals from and supply data signals to the plurality of input/output cells; a plurality of subarray decoders and corresponding configurable interconnect circuits coupled to the configurable logic array, the subarray decoders programmably connectable by the corresponding configurable interconnect circuits to corresponding subarrays in said set of subarrays and decoding address signals from the interconnect structures of the configurable logic array to address memory elements in corresponding subarrays; and a plurality of subarray I/O path circuits and corresponding configurable interconnect circuits coupled to the configurable logic array, the subarray I/O path circuits programmably connectable by the corresponding configurable interconnect circuits to corresponding subarrays of said set of subarrays and providing input and output data signals between the interconnect structures of the configurable logic array and addressed memory elements in corresponding subarrays.

Claim 10

The programmable logic device of claim 7, wherein the configurable interconnect circuits having corresponding subarray decoders include: a programmable switch connected to the configurable logic array and to said corresponding subarray decoder, the programmable switch including inputs connected to the configurable logic array, and including outputs connected to the configurable logic array, and outputs connected to the subarray decoder for said subarray of the memory array.

Claim 11

The programmable logic device of claim 7, wherein the configurable interconnect circuits having corresponding subarray I/O path circuits, include: a programmable switch connected to the configurable logic array and to said corresponding subarray decoder, the programmable switch including inputs connected to the logic cell array, and inputs connected to the data I/O path for said subarray of the memory array, and including outputs connected to the logic cell array, and outputs connected to said subarray I/O path circuit for said subarray of the memory array.

Claim 12

The programmable logic device of claim 7, wherein the configurable logic cells comprise programmable elements configurable in response to data in the memory array to provide a storage element and a logic function.

Claim 13

The programmable logic device of claim 7, wherein the memory array comprises an array of static random access memory cells.

Claim 14

The programmable logic device of claim 7, wherein the subarrays of the configurable logic array to which members of said set of subarrays correspond, include respectively 256 or fewer configurable logic cells, and said set of subarrays includes 4 or more members.

Claim 15

The programmable logic device of claim 7, wherein said set of subarrays includes 16 or more members.

Claim 16

A programmable logic device, comprising: a plurality of input/output cells; a configurable logic array of configurable logic cells and interconnect structures coupled with the plurality of input/output cells; a configuration memory, coupled with the configuration logic array and the plurality of input/output cells, such that the configuration memory stores data to program the configurable logic array, said configuration memory including a set, having more than one member, of subarrays of addressable static random access memory (SRAM) elements, members of said set coupled with corresponding subarrays of the configurable logic array and defining logic functions of corresponding subarrays of the configurable logic array; global memory access logic coupled with the configuration memory and the plurality of input/output cells, the memory access logic including address decode logic configurable to receive address signals from the plurality of input/output cells and in response select addressed SRAM elements in the configuration memory, and memory data path logic configurable to receive data signals from the plurality of input/output cells and the configurable logic array for writing to addressed SRAM elements, and configurable to supply data signals read from addressed SRAM elements to the plurality of input/output cells and the configurable logic array; a plurality of subarray decoders with corresponding configurable interconnect circuits coupled to the configurable logic array, the subarray decoders programmably connectable under control of the configuration memory by the corresponding configurable interconnect circuits to corresponding subarrays in said set of subarrays and decoding address signals from the interconnect structures of the configurable logic array to address SRAM elements in corresponding subarrays; a plurality of subarray I/O path circuits and corresponding configurable interconnect circuits coupled to the configurable logic array, the subarray I/O path circuits programmably connectable by the corresponding configurable interconnect circuits to corresponding subarrays of said set of subarrays and providing input and output data signals between the interconnect structures of the configurable logic array and addressed SRAM elements in corresponding subarrays; wherein the configurable interconnect circuits having corresponding subarray decoders include a programmable switch including inputs connected to the configurable logic array, and including outputs connected to the configurable logic array, and outputs connected to the subarray decoder for the corresponding subarray of the configuration memory; and wherein the configurable interconnect circuits having corresponding subarray I/O path circuits include a programmable switch including inputs connected to the logic cell array and inputs connected to the data I/O path for the corresponding subarray of the configurable memory, and including outputs connected to the logic cell array and outputs connected to said subarray I/O path circuit for the corresponding subarray of the configurable memory.

Claim 17

A programmable logic device, comprising: a plurality of input/output cells; a configurable logic array of configurable logic cells and interconnect structures coupled with the plurality of input/output cells; a configuration memory, coupled with the configuration logic array and the plurality of input/output cells, such that the configuration memory stores data to program the configurable logic array, said configuration memory including a set, having more than one member, of subarrays of addressable static random access memory (SRAM) elements, members of said set coupled with corresponding subarrays of the configurable logic array and defining logic functions of corresponding subarrays of the configurable logic array; global memory access logic coupled with the configuration memory and the plurality of input/output cells, the memory access logic including address decode logic configurable to receive address signals from the plurality of input/output cells and in response select addressed SRAM elements in the configuration memory, and memory data path logic configurable to receive data signals from the plurality of input/output cells and the configurable logic array for writing to addressed SRAM elements, and configurable to supply data signals read from addressed SRAM elements to the plurality of input/output cells and the configurable logic array; a plurality of subarray decoders with corresponding configurable interconnect circuits coupled to the configurable logic array, the subarray decoders programmably connectable under control of the configuration memory by the corresponding configurable interconnect circuits to corresponding subarrays in said set of subarrays and decoding address signals from the interconnect structures of the configurable logic array to address SRAM elements in corresponding subarrays; a plurality of subarray I/O path circuits and corresponding configurable interconnect circuits coupled to the configurable logic array, the subarray I/O path circuits programmably connectable by the corresponding configurable interconnect circuits to corresponding subarrays of said set of subarrays and providing input and output data signals between the interconnect structures of the configurable logic array and addressed SRAM elements in corresponding subarrays; wherein the configurable interconnect circuits having corresponding subarray decoders include a programmable switch including inputs connected to the configurable logic array, and including outputs connected to the configurable logic array, and outputs connected to the subarray decoder for the corresponding subarray of the configuration memory; and wherein the configurable interconnect circuits having corresponding subarray I/O path circuits include a programmable switch including inputs connected to the logic cell array and inputs connected to the data I/O path for the corresponding subarray of the configurable memory, and including outputs connected to the logic cell array and outputs connected to said subarray I/O path circuit for the corresponding subarray of the configurable memory.

Claim 18

The programmable logic device of claim 14, wherein the subarrays of the configurable logic array to which members of said set of subarrays correspond, include respectively 256 or fewer configurable logic cells, and said set of subarrays includes 4 or more members.

Claim 19

The programmable logic device of claim 14, wherein said set of subarrays includes 16 or more members.

Claim 20

The programmable logic device of claim 14, wherein the configurable logic cells comprise programmable elements configurable in response to data in the configuration memory to provide a storage element and a logic function.