Patent US5801427A successfully refreshed from Google Patents.
US5801427A
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US
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Semiconductor device having a polycide structure
Assignee: Mitsubishi Electric Corp
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Filing: 1997-06-11
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Granted: 1998-09-01
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Expires: 2017-06-11
Abstract
Abstract In a semiconductor device having a polycide structure located on a stepped portion, halation during formation of a resist pattern is prevented, and oxidation of an upper surface of a high-melting-point metal silicide layer is prevented during formation of an interlayer insulating film on the polycide structure. In this semiconductor device, an upper layer which is formed of one layer selected from the group consisting of an amorphous silicon layer, a polycrystalline silicon layer, a TiN layer and a TiW layer is formed on the high-melting-point metal silicide layer forming the polycide structure. This effectively suppresses reflection of light beams by the upper layer located at the stepped portion during exposure for forming the resist pattern on the upper layer. Thereby, formation of a notch at the resist pattern is prevented, and the resist pattern is accurately formed to have a designed pattern. The upper layer made of the amorphous silicon layer or polycrystalline silicon layer prevents formation of an oxide layer at an upper surface of the high-melting-point metal silicide layer due to oxydation by Oxygen carried to the inside of the CVD furnace from the outside during formation of an interlayer insulating film covering the polycide structure.
Inventors
- 👤 Shigeru Shiratake
- 👤 Kaoru Motonami
- 👤 Satoshi Hamamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:04
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D64/01; H10D64/011; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10D64/60; H10D64/66; H10D64/661; H10D64/662; H10D64/663; H10P; H10P76/00; H10P76/20; H10P76/204; H10P76/2041; H10P76/2043; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/066; H10D30/601
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
195 words
A semiconductor device comprising: a stepped portion formed on a semiconductor substrate; a first polycrystalline silicon layer having a first portion and a second portion located on and elevated by said stepped portion with respect to the first portion; a high-melting-point metal silicide layer formed on said first polycrystalline silicon layer; and an upper layer formed on said high-melting-point metal silicide layer and formed of one layer selected from the group consisting of an amorphous silicon layer, a polycrystalline silicon layer, a TiN layer and a TiW layer, wherein said first polycrystalline silicon layer, said high-melting-point metal silicide layer and said upper layer form a gate electrode layer of a three-layer structure, said stepped portion is located at a side end of an element isolating and insulating film formed on a main surface of said semiconductor substrate, a side wall insulating film is formed in contact with at least side surfaces of said polycrystalline silicon layer and said high-melting-point metal silicide layer in a section along a channel length direction of said gate electrode layer, and a concavity is formed in the main surface of said semiconductor substrate located outside said side wall insulating film.
Claim 2
Dependent Claim
195 words
A semiconductor device comprising: a stepped portion formed on a semiconductor substrate; a first polycrystalline silicon layer having a first portion and a second portion located on and elevated by said stepped portion with respect to the first portion; a high-melting-point metal silicide layer formed on said first polycrystalline silicon layer; and an upper layer formed on said high-melting-point metal silicide layer and formed of one layer selected from the group consisting of an amorphous silicon layer, a polycrystalline silicon layer, a TiN layer and a TiW layer, wherein said first polycrystalline silicon layer, said high-melting-point metal silicide layer and said upper layer form a gate electrode layer of a three-layer structure, said stepped portion is located at a side end of an element isolating and insulating film formed on a main surface of said semiconductor substrate, a side wall insulating film is formed in contact with at least side surfaces of said polycrystalline silicon layer and said high-melting-point metal silicide layer in a section along a channel length direction of said gate electrode layer, and a concavity is formed in the main surface of said semiconductor substrate located outside said side wall insulating film.
Claim 3
Dependent Claim
51 words
The semiconductor device according to claim 1, wherein said first polycrystalline silicon layer, said high-melting-point metal silicide layer and said upper layer form an interconnection layer of a three-layer structure, and said stepped portion is located at a surface of insulating film covering a conductive layer formed on said semiconductor substrate.
Claim 4
Dependent Claim
51 words
The semiconductor device according to claim 1, wherein said first polycrystalline silicon layer contains impurity of a first conductivity type, said upper layer is an amorphous silicon layer or a polycrystalline silicon layer, and said upper layer contains impurity of the same first conductivity type as said first polycrystalline silicon layer.
Claim 5
Dependent Claim
26 words
The semiconductor device according to claim 1, wherein said first polycrystalline silicon layer has a thickness not smaller than that of said high-melting-point metal silicide layer.
Claim 6
Dependent Claim
151 words
A semiconductor device comprising: a semiconductor substrate having a main surface; a pair of source/drain regions formed on the main surface of said semiconductor substrate and spaced by a predetermined distance from each other to define a channel region therebetween; a first polycrystalline silicon layer formed on said channel region with a gate insulating film therebetween; a high-melting-point metal silicide layer formed on said first polycrystalline silicon layer; an upper layer formed on said high-melting-point metal silicide layer and formed of one layer selected from the group consisting of an amorphous silicon layer, a TiN layer and a TiW layer; a side wall insulating film formed in contact with at least side surfaces of said first polycrystalline silicon layer and said high-melting-point metal silicide layer; and a concavity formed in the main surface of said semiconductor substrate located outside an end of a lower surface of said side wall insulating film.
Claim 7
Dependent Claim
151 words
A semiconductor device comprising: a semiconductor substrate having a main surface; a pair of source/drain regions formed on the main surface of said semiconductor substrate and spaced by a predetermined distance from each other to define a channel region therebetween; a first polycrystalline silicon layer formed on said channel region with a gate insulating film therebetween; a high-melting-point metal silicide layer formed on said first polycrystalline silicon layer; an upper layer formed on said high-melting-point metal silicide layer and formed of one layer selected from the group consisting of an amorphous silicon layer, a TiN layer and a TiW layer; a side wall insulating film formed in contact with at least side surfaces of said first polycrystalline silicon layer and said high-melting-point metal silicide layer; and a concavity formed in the main surface of said semiconductor substrate located outside an end of a lower surface of said side wall insulating film.
Claim 8
Dependent Claim
45 words
The semiconductor device according to claim 5, wherein said first polycrystalline silicon layer contains impurity of a first conductivity type, said upper layer is an amorphous silicon layer, and said upper layer contains impurity of the same first conductivity type as said polycrystalline silicon layer.
Claim 9
Dependent Claim
26 words
The semiconductor device according to claim 5, wherein said first polycrystalline silicon layer has a thickness not smaller than that of said high-melting-point metal silicide layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-08-31 | 2002-03-02 | 2002-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-31 | 2006-03-02 | 2006-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-31 | 2010-03-02 | 2010-09-01 | $7700.00 | Window Closed / Lapsed |