US5798635A
Expired / Lapsed
US
⏱️ 0.0 years remaining
One pin error amplifier and switched soft-start for an eight pin PFC-PWM combination integrated circuit converter controller
Assignee: Fairchild Semiconductor Corp
•
Filing: 1997-02-06
•
Granted: 1998-08-25
•
Expires: 2017-02-06
Abstract
Abstract A combination PFC-PWM integrated circuit converter controller having a power factor correction stage and a pulse-width modulation stage. The power factor correction stage provides unity power factor and a regulated intermediate output voltage by sensing a current in the power factor correction circuit and by sensing the regulated intermediate output voltage in a voltage control loop. The regulated intermediate output voltage is sensed by an error amplifier that includes a current mirror. A dc supply voltage for powering the integrated circuit is generated that is representative of the regulated intermediate output voltage. The dc supply voltage is sensed for an overvoltage protection function. By sensing the intermediate regulated output voltage in the voltage control loop and by sensing the dc supply voltage for overvoltage protection, a component failure is less likely to affect both functions than if a single voltage was sensed for both functions. The pulse-width modulation stage waits a predetermined delay time after start up for the output voltage to rise before beginning the pulse-width modulation function. The delay time is determined by an amount of time taken to charge a capacitor to a predetermined voltage after start up. The capacitor is charged by a current source that is switched on and off according to a clock signal such that the capacitor is charged only a portion of time. Therefore, a larger current source may be used than otherwise which results in more reliable control of the delay time.
Inventors
- 👤 Jeffrey H. Hwang
- 👤 Donald Yu
- 👤 Calvin Hsu
- 👤 Alland Chee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 16:16
CPC Classifications
H; H02; H02M; H02M1/00; H02M1/42; H02M1/4208; H02M1/4225; H02M1/0067; H02M1/007; Y; Y02; Y02B; Y02B70/00; Y02B70/10; Y02P; Y02P80/00; Y02P80/10
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
110 words
A converter controller for controlling a converter, the converter having a power factor correction stage, the power factor correction stage having a control loop for forming a regulated output voltage at an output node wherein the control loop comprises an error amplifier, the error amplifier comprising: a. a first resistor having a first terminal and a second terminal wherein the first terminal of the first resistor is coupled to the output node of the power factor correction stage and the second terminal of the first resistor forms an output node of the error amplifier; and b. means for drawing a constant current from the output node of the error amplifier.
Claim 2
Dependent Claim
110 words
A converter controller for controlling a converter, the converter having a power factor correction stage, the power factor correction stage having a control loop for forming a regulated output voltage at an output node wherein the control loop comprises an error amplifier, the error amplifier comprising: a. a first resistor having a first terminal and a second terminal wherein the first terminal of the first resistor is coupled to the output node of the power factor correction stage and the second terminal of the first resistor forms an output node of the error amplifier; and b. means for drawing a constant current from the output node of the error amplifier.
Claim 3
Dependent Claim
100 words
The converter controller according to claim 1 wherein the power factor correction stage comprises a switch coupled to a control a current in an inductor for charging a capacitor to the regulated output voltage and wherein the control loop further comprises: a. means for forming a voltage representative of current in the inductor; b. means for integrating a voltage generated at an output node of the error amplifier for forming an integrated voltage; and c. means for comparing the integrated voltage to the voltage representative of the current in the inductor, the means for comparing coupled to control the switch.
Claim 4
Dependent Claim
19 words
The converter controller according to claim 1 wherein the means for drawing a constant current comprises a current mirror.
Claim 5
Dependent Claim
129 words
The converter controller according to claim 1 wherein the means for drawing a constant current comprises: a. a current source for generating a constant current; b. a first transistor having a base, a collector and an emitter wherein the collector of the first transistor is coupled to the base of the first transistor and to the current source; and c. a second transistor having a base, a collector and an emitter wherein the base of the second transistor is coupled to the base of the first transistor and to the collector of the second transistor and the emitter of the second transistor is coupled to the emitter of the first transistor and wherein the collector of the second transistor is coupled to the second terminal of the first resistor.
Claim 6
Dependent Claim
129 words
The converter controller according to claim 1 wherein the means for drawing a constant current comprises: a. a current source for generating a constant current; b. a first transistor having a gate, a drain and a source wherein the drain of the first transistor is coupled to the gate of the first transistor and to the current source; and c. a second transistor having a gate, a drain and a source wherein the gate of the second transistor is coupled to the gate of the first transistor and to the drain of the second transistor and the source of the second transistor is coupled to the source of the first transistor and wherein the drain of the second transistor is coupled to the second terminal of the first resistor.
Claim 7
Dependent Claim
74 words
The converter controller according to claim 1 wherein the converter further comprises a circuit for forming a supply voltage for the converter controller wherein the circuit for forming the supply voltage is coupled to the power factor correction stage and wherein the converter controller comprises an overvoltage protection circuit coupled to monitor the supply voltage wherein the overvoltage protection circuit and the voltage control loop each prevent the regulated output voltage from becoming excessive.
Claim 8
Dependent Claim
33 words
The converter controller according to claim 1 wherein the converter further comprises a pulse-width modulation stage coupled to the output node of the power factor correction stage for receiving the regulated output voltage.
Claim 9
Dependent Claim
41 words
The converter controller according to claim 7 wherein the pulse-width modulation stage comprises means for preventing a voltage regulating function of the pulse-width modulation stage from beginning until a after predetermined amount of time has elapsed from start-up of the converter.
Claim 10
Dependent Claim
21 words
The converter controller according to claim 8 wherein the converter controller is an integrated circuit having no more than eight pins.
Claim 11
Dependent Claim
35 words
The converter controller according to claim 8 wherein the means for preventing comprises a current source for charging a capacitor to a predetermined voltage wherein the current source only charges the capacitor during periodic intervals.
Claim 12
Dependent Claim
20 words
The converter controller according to claim 1 further comprising a compensation element coupled to the output of the error amplifier.
Claim 13
Dependent Claim
21 words
The converter controller according to claim 11 wherein the compensation element comprises a second resistor and a capacitor coupled in series.
Claim 14
Dependent Claim
162 words
A converter controller for controlling a converter, the converter comprising a power factor correction stage wherein the power factor correction stage comprises means for switching coupled to alternately charge a first inductor and to discharge the first inductor into an output capacitor for forming a regulated output voltage across the output capacitor and means for forming a supply voltage for providing power to the converter controller wherein the means for forming the supply voltage comprises a second inductor inductively coupled to the first inductor, and wherein the converter controller comprises: a. means for controlling the means for switching in a feedback loop for maintaining the regulated output voltage at a desired level, the means for controlling coupled to the output capacitor and to the means for switching; and b. means for disabling coupled to the means for switching for disabling the means for switching when a level of voltage formed by the means for forming the supply voltage exceeds a predetermined level.
Claim 15
Dependent Claim
162 words
A converter controller for controlling a converter, the converter comprising a power factor correction stage wherein the power factor correction stage comprises means for switching coupled to alternately charge a first inductor and to discharge the first inductor into an output capacitor for forming a regulated output voltage across the output capacitor and means for forming a supply voltage for providing power to the converter controller wherein the means for forming the supply voltage comprises a second inductor inductively coupled to the first inductor, and wherein the converter controller comprises: a. means for controlling the means for switching in a feedback loop for maintaining the regulated output voltage at a desired level, the means for controlling coupled to the output capacitor and to the means for switching; and b. means for disabling coupled to the means for switching for disabling the means for switching when a level of voltage formed by the means for forming the supply voltage exceeds a predetermined level.
Claim 16
Dependent Claim
158 words
The converter controller according to claim 13 wherein the means for controlling the means for switching in a feedback loop comprises: a. a current source for generating a constant current; b. a first transistor having a base, a collector and an emitter wherein the collector of the first transistor is coupled to the base of the first transistor and to the current source; c. a second transistor having a base, a collector and an emitter wherein the base of the second transistor is coupled to the base of the first transistor and to the collector of the second transistor and the emitter of the second transistor is coupled to the emitter of the first transistor; and d. a resistor having a first terminal and a second terminal wherein the first terminal of the resistor is coupled to receive the regulated output voltage and the second terminal of the resistor is coupled to the collector of the second transistor.
Claim 17
Dependent Claim
155 words
The converter controller according to claim 13 wherein the means for controlling the means for switching comprises: a. a current source for generating a constant current; b. a first transistor having a gate, a drain and a source wherein the drain of the first transistor is coupled to the gate of the first transistor and to the current source; and c. a second transistor having a gate, a drain and a source wherein the gate of the second transistor is coupled to the gate of the first transistor and to the drain of the second transistor and the source of the second transistor is coupled to the source of the first transistor; and d. a resistor having a first terminal and a second terminal wherein the first terminal of the resistor is coupled to receive the regulated output voltage and the second terminal of the resistor is coupled to the drain of the second transistor.
Claim 18
Dependent Claim
78 words
A converter controller for controlling a converter, the converter having a pulse-width modulation stage, the pulse width modulation stage comprising: a. a capacitor; b. means for charging the capacitor with a first current during periodic intervals upon start-up of the converter; c. means for charging the capacitor with a second current during alternate intervals; and d. means for preventing the pulse-width modulation function from beginning until after a voltage across the capacitor has risen to a predetermined level.
Claim 19
Dependent Claim
78 words
A converter controller for controlling a converter, the converter having a pulse-width modulation stage, the pulse width modulation stage comprising: a. a capacitor; b. means for charging the capacitor with a first current during periodic intervals upon start-up of the converter; c. means for charging the capacitor with a second current during alternate intervals; and d. means for preventing the pulse-width modulation function from beginning until after a voltage across the capacitor has risen to a predetermined level.
Claim 20
Dependent Claim
14 words
The converter controller according to claim 16 wherein the second current is substantially zero.
Claim 21
Dependent Claim
167 words
The converter controller according to claim 16 further comprising a power factor correction stage wherein the power factor correction stage comprises: a. means for switching coupled to alternately charge a first inductor and to discharge the first inductor into an output capacitor for forming a regulated output voltage across the output capacitor wherein the pulse-width modulation stage is coupled to the output capacitor for receiving the regulated output voltage; b. means for controlling the means for switching in a feedback loop for maintaining the regulated output voltage at a desired level, the means for controlling coupled to the output capacitor and to the means for switching; c. means for forming a supply voltage for providing power to the converter controller wherein the means for forming comprises a second inductor inductively coupled to the first inductor; and d. means for disabling coupled to the means for switching for disabling the means for switching when a level of voltage formed by the means for forming exceeds a predetermined level.
Claim 22
Dependent Claim
21 words
The converter controller according to claim 18 wherein the converter controller is an integrated circuit having no more than eight pins.
Claim 23
Dependent Claim
154 words
The converter controller according to claim 18 wherein the means for controlling the means for switching comprises: a. a current source for generating a constant current; b. a first transistor having a base, a collector and an emitter wherein the collector of the first transistor is coupled to the base of the first transistor and to the current source; c. a second transistor having a base, a collector and an emitter wherein the base of the second transistor is coupled to the base of the first transistor and to the collector of the second transistor and the emitter of the second transistor is coupled to the emitter of the first transistor; and d. a resistor having a first terminal and a second terminal wherein the first terminal of the resistor is coupled to receive the regulated output voltage and the second terminal of the resistor is coupled to the collector of the second transistor.
Claim 24
Dependent Claim
155 words
The converter controller according to claim 18 wherein the means for controlling the means for switching means comprises: a. a current source for generating a constant current; b. a first transistor having a gate, a drain and a source wherein the drain of the first transistor is coupled to the gate of the first transistor and to the current source; and c. a second transistor having a gate, a drain and a source wherein the gate of the second transistor is coupled to the gate of the first transistor and to the drain of the second transistor and the source of the second transistor is coupled to the source of the first transistor; d. a resistor having a first terminal and a second terminal wherein the first terminal of the resistor is coupled to receive the regulated output voltage and the second terminal of the resistor is coupled to the drain of the second transistor.
Claim 25
Dependent Claim
131 words
An error amplifier having an input node and output node, wherein a change in an input voltage level applied to the input node results in a change in an output voltage formed at the output node wherein the change in the output voltage relative to an expected quiescent value for the output voltage is greater than the change in the input voltage relative to an expect quiescent value for the input voltage, the error amplifier comprising: a. a first resistor having a first terminal and a second terminal wherein the first terminal of the first resistor forms the input node for the error amplifier and the second terminal of the first resistor forms the output node for the error amplifier; and b. means for drawing a constant current through the resistor.
Claim 26
Dependent Claim
131 words
An error amplifier having an input node and output node, wherein a change in an input voltage level applied to the input node results in a change in an output voltage formed at the output node wherein the change in the output voltage relative to an expected quiescent value for the output voltage is greater than the change in the input voltage relative to an expect quiescent value for the input voltage, the error amplifier comprising: a. a first resistor having a first terminal and a second terminal wherein the first terminal of the first resistor forms the input node for the error amplifier and the second terminal of the first resistor forms the output node for the error amplifier; and b. means for drawing a constant current through the resistor.
Claim 27
Dependent Claim
19 words
The error amplifier according to claim 22 wherein the means for drawing a constant current comprises a current mirror.
Claim 28
Dependent Claim
129 words
The error amplifier according to claim 22 wherein the means for drawing a constant current comprises: a. a current source for generating a constant current; b. a first transistor having a base, a collector and an emitter wherein the collector of the first transistor is coupled to the base of the first transistor and to the current source; and c. a second transistor having a base, a collector and an emitter wherein the base of the second transistor is coupled to the base of the first transistor and to the collector of the second transistor and the emitter of the second transistor is coupled to the emitter of the first transistor and wherein the collector of the second transistor is coupled to the second terminal of the first resistor.
Claim 29
Dependent Claim
128 words
The amplifier according to claim 22 wherein the means for drawing a constant current comprises: a. a current source for generating a constant current; b. a first transistor having a gate, a drain and a source wherein the drain of the first transistor is coupled to the gate of the first transistor and to the current source; and c. a second transistor having a gate, a drain and a source wherein the gate of the second transistor is coupled to the gate of the first transistor and to the drain of the second transistor and the source of the second transistor is coupled to the source of the first transistor and wherein the drain of the second transistor is coupled to the second terminal of the first resistor.
Claim 30
Dependent Claim
19 words
The amplifier according to claim 22 further comprising a compensation element coupled to the output of the error amplifier.
Claim 31
Dependent Claim
20 words
The amplifier according to claim 26 wherein the compensation element comprises a second resistor and a capacitor coupled in series.
References Cited (Backward Citations)
US3294981A
Cited
US3603809A
Cited
US4456872A
Cited
US3660753A
Cited
US3883756A
Cited
US4311954A
Cited
US4392103A
Cited
US4407588A
Cited
US4437146A
Cited
JPS6022490A
Cited
US4529927A
Cited
US4731574A
Cited
US4651231A
Cited
US4691159A
Cited
US4677366A
Cited
US4672518A
Cited
US4761725A
Cited
US4672303A
Cited
US4947309A
Cited
US4736151A
Cited
US4929882A
Cited
US4841220A
Cited
US4975823A
Cited
US4845420A
Cited
US4941080A
Cited
US5034873A
Cited
US4920309A
Cited
US5028861A
Cited
US4940929A
Cited
US5146399A
Cited
US5138294A
Cited
US5278490A
Cited
US5485361A
Cited
US5457621A
Cited
US5359281A
Cited
US5457622A
Cited
US5481178A
Cited
US5440473A
Cited
US5461302A
Cited
US5414341A
Cited
US5412308A
Cited
US5434767A
Cited
US5450000A
Cited
US5552695A
Cited
US5532577A
Cited
US5491445A
Cited
US5565761A
Cited
US5502370A
Cited
US5479089A
Cited
US5627460A
Cited
US5592071A
Cited
US5568041A
Cited
US5617306A
Cited
US5592128A
Cited
US5610502A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-24 | 2002-02-23 | 2002-08-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-24 | 2006-02-23 | 2006-08-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-24 | 2010-02-23 | 2010-08-25 | $7700.00 | Window Closed / Lapsed |