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US5592071A
Expired / Lapsed
US
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Method and apparatus for self-regeneration synchronous regulator
Assignee: Dell USA LP
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Filing: 1995-01-11
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Granted: 1997-01-07
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Expires: 2015-01-11
Abstract
Abstract A synchronous regulator circuit including a transformer having a secondary inductor magnetically coupled to a primary inductor, where the secondary inductor is coupled to control a synchronous power switch. The secondary inductor operates to drive the synchronous power switch using self-regeneration during a flux reversal phase of each cycle. A timing circuit or simple pulse width modulation circuit (PWM) turns on the primary switch and turns off the synchronous switch during a power phase of each cycle, and then turns off the primary switch during the flux reversal phase of each cycle. The flux reversal of the secondary inductor drives the synchronous switch on, thereby achieving synchronous operation without an expensive dual output PWM. The present invention is illustrated using both a buck and a boost topology. A third switch is preferably used to clamp the synchronous switch off during the power phase.
Inventors
- 👤 Alan E. Brown
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 00:07
CPC Classifications
H; H02; H02M; H02M1/00; H02M1/38; G; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/62
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
144 words
A synchronous regulator circuit, comprising: a transformer having first and second magnetically coupled inductors, said first inductor for transferring power to an output of the synchronous regulator circuit; means for providing a DC source voltage; a first switch having a current path coupled to said first inductor and said DC source voltage providing means, said power switch having a control terminal; a second switch having a current path coupled to said first inductor and a control terminal coupled to said second inductor; and a timing circuit coupled to said first and second switches for turning on said first switch and turning off said second switch during a power phase and for turning off said first switch during a flux reversal phase of each cycle, wherein flux reversal of said second inductor turns on said second switch during said flux reversal phase of each cycle.
Claim 2
Dependent Claim
144 words
A synchronous regulator circuit, comprising: a transformer having first and second magnetically coupled inductors, said first inductor for transferring power to an output of the synchronous regulator circuit; means for providing a DC source voltage; a first switch having a current path coupled to said first inductor and said DC source voltage providing means, said power switch having a control terminal; a second switch having a current path coupled to said first inductor and a control terminal coupled to said second inductor; and a timing circuit coupled to said first and second switches for turning on said first switch and turning off said second switch during a power phase and for turning off said first switch during a flux reversal phase of each cycle, wherein flux reversal of said second inductor turns on said second switch during said flux reversal phase of each cycle.
Claim 3
Dependent Claim
34 words
The synchronous regulator circuit of claim 1, wherein said timing circuit includes: a third switch coupled to said control terminal of said second switch for clamping said second switch off during said power phase.
Claim 4
Dependent Claim
23 words
The synchronous regulator circuit of claim 1, wherein said transformer and said first and second switches are coupled to implement a buck regulator.
Claim 5
Dependent Claim
67 words
The synchronous regulator circuit of claim 3, wherein said current path of said first switch is coupled in series between said DC source voltage providing means and said first inductor of said transformer, wherein said first inductor is coupled in series between said first switch and said output and said second inductor is coupled in series between said output and said control terminal of said second switch.
Claim 6
Dependent Claim
30 words
The synchronous regulator circuit of claim 4, wherein said current path of said second switch is coupled between ground and the junction of said first switch and said first inductor.
Claim 7
Dependent Claim
37 words
The synchronous regulator circuit of claim 3, wherein said timing circuit includes a timer for asserting a pulse width modulated signal to said control terminal of said first switch for turning on and off said first switch.
Claim 8
Dependent Claim
44 words
The synchronous regulator circuit of claim 6, wherein said timing circuit further includes a third switch coupled to said second switch and receiving said pulse width modulated signal, wherein said third switch turns off said second switch while said first switch is turned on.
Claim 9
Dependent Claim
14 words
The synchronous regulator circuit of claim 7, wherein said third switch is a MOSFET.
Claim 10
Dependent Claim
14 words
The synchronous regulator circuit of claim 6, wherein said timer is a 555-type timer.
Claim 11
Dependent Claim
15 words
The synchronous regulator circuit of claim 1, wherein said first and second switches are MOSFETs.
Claim 12
Dependent Claim
19 words
The synchronous regulator circuit of claim 10, wherein said feedback circuit includes a voltage divider and a shunt regulator.
Claim 13
Dependent Claim
30 words
The synchronous regulator circuit of claim 1, further comprising a feedback circuit coupled between said output of the synchronous regulator circuit and said timing circuit for sensing the output voltage.
Claim 14
Dependent Claim
23 words
The synchronous regulator circuit of claim 1, wherein said transformer and said first and second switches are coupled to implement a boost regulator.
Claim 15
Dependent Claim
30 words
The synchronous regulator circuit of claim 13, further comprising a feedback circuit coupled between said output of the synchronous regulator circuit and said timing circuit for sensing the output voltage.
Claim 16
Dependent Claim
39 words
The synchronous regulator circuit of claim 14, wherein said timing circuit includes a feedback input receiving a feedback signal from said feedback circuit for varying the duty cycle of a pulse width modulated signal provided by said timing circuit.
Claim 17
Dependent Claim
33 words
The synchronous regulator circuit of claim 13, wherein said timing circuit includes a third switch coupled to said second switch for turning off said second switch while said first switch is turned on.
Claim 18
Dependent Claim
14 words
The synchronous regulator circuit of claim 16, wherein said third switch is a MOSFET.
Claim 19
Dependent Claim
36 words
The synchronous regulator circuit of claim 16, wherein said timing circuit asserts a pulse width modulated signal and includes a fourth switch receiving said pulse width modulated signal for turning on and off said third switch.
Claim 20
Dependent Claim
29 words
The synchronous regulator circuit of claim 18, wherein said timing circuit includes a fifth switch receiving said pulse width modulated signal for turning on and off said first switch.
Claim 21
Dependent Claim
63 words
The synchronous regulator circuit of claim 1, wherein said current path of said first switch is coupled in series between said first inductor and ground, wherein said first inductor is coupled in series between said DC source voltage providing means and said first switch and wherein said current path of said second switch is coupled in series between said transformer and said output.
Claim 22
Dependent Claim
28 words
The synchronous regulator circuit of claim 20, wherein said second inductor is coupled between one end of said current path and said control terminal of said second switch.
Claim 23
Dependent Claim
140 words
A synchronous switching circuit for a regulator circuit including a pulse width modulation circuit for switching between power and flyback phases, a DC source voltage, a primary power inductor, a primary power switch controlled by the pulse width modulation for transferring power from the DC source voltage to the power inductor and a feedback circuit coupled between an output of the regulator circuit and the pulse width modulation circuit for defining the level of output voltage, said synchronous switching circuit comprising: a secondary inductor for magnetically coupling to the power inductor; and a synchronous switch circuit for coupling to the pulse width modulation circuit and coupled to said secondary inductor; wherein said synchronous switch circuit is turned off while the power switch is turned on and is turned on by said secondary inductor during flux reversal of the power inductor.
Claim 24
Dependent Claim
140 words
A synchronous switching circuit for a regulator circuit including a pulse width modulation circuit for switching between power and flyback phases, a DC source voltage, a primary power inductor, a primary power switch controlled by the pulse width modulation for transferring power from the DC source voltage to the power inductor and a feedback circuit coupled between an output of the regulator circuit and the pulse width modulation circuit for defining the level of output voltage, said synchronous switching circuit comprising: a secondary inductor for magnetically coupling to the power inductor; and a synchronous switch circuit for coupling to the pulse width modulation circuit and coupled to said secondary inductor; wherein said synchronous switch circuit is turned off while the power switch is turned on and is turned on by said secondary inductor during flux reversal of the power inductor.
Claim 25
Dependent Claim
37 words
The synchronous switching circuit of claim 22, wherein said synchronous switch circuit comprises: a first switch for coupling to the pulse width modulation circuit; and a second switch coupled to said first switch and said secondary inductor.
Claim 26
Dependent Claim
14 words
The synchronous switch circuit of claim 23, wherein said second switch comprises a MOSFET.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-01-07 | 2000-07-08 | 2001-01-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-01-07 | 2004-07-08 | 2005-01-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-01-07 | 2008-07-08 | 2009-01-07 | $7700.00 | Window Closed / Lapsed |