Abstract An electronic timer having an oscillator, a counter which counts outputs of the oscillator up to a predetermined count value and thereupon generates an output, and an output circuit for generating an output signal in response to the output from the counter, the oscillator comprising a first terminal for connection with a time constant circuit consisting of a resistor and a capacitor, a second terminal supplied with a reference voltage, a dividing resistance circuit for developing a first upper limit voltage and a lower limit voltage, a first upper limit comparator for comparing a potential at the first terminal with the first upper limit voltage, a second upper limit comparator for comparing the potential at first terminal with the reference voltage, an OR-circuit for receiving outputs from the first and second upper limit comparators, a lower limit comparator for comparing the potential at the first terminal with the lower limit voltage, a flip-flop which is set by an output from the OR-circuit and reset by an output from the lower limit comparator, and a transistor for discharging the capacitor in response to an output generated from the flip-flop.
An electronic timer having an oscillator formed on a single IC chip, a time constant circuit connected to said oscillator and consisting of a resistor and capacitor connected in series, a counter which counts outputs of said oscillator up to a predetermined count value and thereupon generates an output, and an output circuit for generating an output signal in response to said output from the counter, said oscillator comprising a first input terminal for connection with said time constant circuit, a second input terminal adapted to be connected to a variable resistance for supplying a reference voltage, a dividing resistance circuit for developing a first upper limit voltage and a lower limit voltage, a first upper limit comparator connected to said resistance circuit and to said first terminal for comparing a potential at said first terminal with said first upper limit voltage, a second upper limit comparator connected to said second terminal for comparing said potential at first terminal with said reference voltage, an OR-circuit for receiving outputs from said first and second upper limit comparators, a lower limit comparator connected to said resistance circuit and to said first terminal for comparing the potential at said first terminal with said lower limit voltage, a flip-flop which is set by an output from said OR-circuit and reset by an output from said lower limit comparator, and a transistor for discharging said capacitor in response to an output generated from said flip-flop.
Claim 2
Dependent Claim
240 words
An electronic timer having an oscillator formed on a single IC chip, a time constant circuit connected to said oscillator and consisting of a resistor and capacitor connected in series, a counter which counts outputs of said oscillator up to a predetermined count value and thereupon generates an output, and an output circuit for generating an output signal in response to said output from the counter, said oscillator comprising a first input terminal for connection with said time constant circuit, a second input terminal adapted to be connected to a variable resistance for supplying a reference voltage, a dividing resistance circuit for developing a first upper limit voltage and a lower limit voltage, a first upper limit comparator connected to said resistance circuit and to said first terminal for comparing a potential at said first terminal with said first upper limit voltage, a second upper limit comparator connected to said second terminal for comparing said potential at first terminal with said reference voltage, an OR-circuit for receiving outputs from said first and second upper limit comparators, a lower limit comparator connected to said resistance circuit and to said first terminal for comparing the potential at said first terminal with said lower limit voltage, a flip-flop which is set by an output from said OR-circuit and reset by an output from said lower limit comparator, and a transistor for discharging said capacitor in response to an output generated from said flip-flop.
Claim 3
Dependent Claim
26 words
An electronic timer according to claim 1, wherein said reference voltage is a second upper limit voltage between said first upper and said lower limit voltages.