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US3883756A Expired / Lapsed US ⏱️ 0.0 years remaining

Pulse generator with automatic timing adjustment for constant duty cycle

Assignee: Unisys Corp
•
Filing: 1973-12-27
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Granted: 1975-05-13
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Expires: 1993-12-27
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Abstract

Abstract A circuit for generating a waveform comprising a train of rectangular pulses in response to a train of trigger signals such that the duration of each rectangular pulse is a precise multiple of the time lapse between pulses, in spite of variation in the waveform''s absolute period. The circuit employs a flip-flop set by a trigger signal and timed to reset by a ramp signal-toreference voltage comparison circuit. The output of the flip-flop is subject to continuous adjustment by the circuit to achieve the desired waveform, and to this end is monitored by a first discharging current source producing a fixed current and activated by the set state and a second charging current source producing a fixed multiple, the desired time lapse multiple, of the first current and activated by the reset state. Should one of the current sources be kept on too long by a deviation of the relative pulse (set) and lapse (reset) durations from the desired multiple, a capacitor driven by the two sources will be relatively over-or undercharged, depending on which current source is overactivated, and the charge and hence voltage change will be monitored to adjust the reference voltage to return to the desired timing multiple.

Inventors

  • 👤 Thomas J Dragon

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 00:21
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/01; H03K3/015; H03K5/00; H03K5/156; H03K5/1565

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 141 words
Circuitry for generating a train of substantially rectangular pulses in response to a train of trigger signals comprising: flip-flop means having set and reset states and an output, said output being set by each of said trigger signals, to initiate a said rectangular pulse; means for generating ramp voltage signals having identical initial levels, each generation being activated when said flipflop means is set and deactivated when said flip-flop means is reset; reference means for generating a reference voltage level; means for resetting said flip-flop upon equality of said reference and ramp voltages to terminate a said rectangular pulse; and means for automatically varying said reference voltage level in accordance with the variation in the time lapse between said pulses so as to maintain the duration of said rectangular pulses as a constant multiple of said time lapse between said pulses.
Claim 2
Dependent Claim 141 words
Circuitry for generating a train of substantially rectangular pulses in response to a train of trigger signals comprising: flip-flop means having set and reset states and an output, said output being set by each of said trigger signals, to initiate a said rectangular pulse; means for generating ramp voltage signals having identical initial levels, each generation being activated when said flipflop means is set and deactivated when said flip-flop means is reset; reference means for generating a reference voltage level; means for resetting said flip-flop upon equality of said reference and ramp voltages to terminate a said rectangular pulse; and means for automatically varying said reference voltage level in accordance with the variation in the time lapse between said pulses so as to maintain the duration of said rectangular pulses as a constant multiple of said time lapse between said pulses.
Claim 3
Dependent Claim 72 words
The pulse-generating circuitry of claim 1 wherein said automatic duration varying means comprises: means activated only by said set state for producing a first constant current; means activated only by said reset state for producing a second current having a magnitude which is said multiple of said first current; and charge accumulating means oppositely charged by said first and second currents for maintaining an average charge level for controlling said reference level.
Claim 4
Dependent Claim 68 words
The pulse-generating circuitry of claim 2 wherein said first and second current producing means each includes: a driver transistor having two main current-carrying electrodes and a control electrode, the first of said current-carrying electrodes being connected to said accumulating means; and means connected to the second current carrying electrode and said control electrode for actuating said driver transistor and holding a constant actuating voltage on said control electrode.
Claim 5
Dependent Claim 56 words
The pulse-generating circuit of claim 3 wherein said actuating and holding means includes: a switching transistor connected for supplying a constant voltage at one of its electrodes upon actuation; a zener diode connected between said constant voltage electrode and said control electrode; and a resistor connected between said second current-carrying electrode and said constant voltage electrode.
Claim 6
Dependent Claim 25 words
The pulse generating circuit of claim 2 further including a transistor configured as an emitter-follower for coupling said charge accumulating means to said reference means.

References Cited (Backward Citations)

US3484624A Cited
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US3601708A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1978-05-12 1978-11-11 1979-05-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1982-05-12 1982-11-11 1983-05-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1986-05-12 1986-11-11 1987-05-13 $7700.00 Window Closed / Lapsed

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