US5796624A
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Method and apparatus for designing circuits for wave pipelining
Assignee: Research Foundation of the State University of New York
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Filing: 1997-02-06
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Granted: 1998-08-18
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Expires: 2017-02-06
Abstract
Abstract A family of CFET logic circuits useful for wave-pipeline systems is described, and a method to design same. The invention uses complementary transmission gates and pull-up or pull-down transistors to achieve a family of CFET logic circuits which include AND, NAND, OR, NOR, XOR, XNOR, select, select-invert, invert, and not-invert functions. Each circuit is tuned to provide substantially equal delays, high-quality ones and zeros, and substantially equal rise and fall times, for every combination of input-state transition and output-state transition.
Inventors
- 👤 Ramalingam Sridhar
- 👤 Zhang Xuguang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 07:55
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/20; H03K19/21; H03K19/215; G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/327; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/506; G06F7/508; G06F7/60; G06F7/607; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/0948; H03K19/173; H03K19/1733; H03K19/1737; G06F2207/00; G06F2207/506; G06F2207/5063
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
123 words
A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern, the method comprising the steps: forming a map of the desired logic function; assigning cells of the map into pairs of map cells; implementing a transmission gate for each one, if any, of the pairs of map cells that has one high value and one low value; implementing a pull transistor for each one, if any, of the pairs of map cells having values that are equal; and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern.
Claim 2
Independent Claim
123 words
A method for designing a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern, the method comprising the steps: forming a map of the desired logic function; assigning cells of the map into pairs of map cells; implementing a transmission gate for each one, if any, of the pairs of map cells that has one high value and one low value; implementing a pull transistor for each one, if any, of the pairs of map cells having values that are equal; and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern.
Claim 3
Dependent Claim
13 words
The method according to claim 1, wherein the map is a Karnaugh map.
Claim 4
Dependent Claim
20 words
The method according to claim 2, wherein the pairs of cells are pairs of adjacent cells in the Karnaugh map.
Claim 5
Dependent Claim
53 words
The method according to claim 1, wherein the step of implementing a pull-up or a pull-down transistor for each one, if any, of the pairs of map cells having values that are equal includes implementing a pull-up transistor if both values are high and implementing a pull-down transistor if both values are low.
Claim 6
Dependent Claim
79 words
The method according to claim 2, wherein the step of adjusting electrical properties comprises the steps of: determining a ratio of N-type transistor size to P-type transistor size of a first transmission gate to ensure substantially equal rise and fall times of the transmission gate; and determining a ratio of the first transmission gate size to the first pull transistor size to ensure substantially equal rise and fall times of the first transmission gate and the first pull transistor.
Claim 7
Dependent Claim
145 words
The method according to claim 1, further comprising the steps of: for the transmission gate, if any, coupling a first terminal to a first input signal, coupling a second terminal to a node, and coupling a gate to a second input signal; for the pull transistor, if any, coupling a first terminal to a voltage source, coupling a second terminal to the node, and coupling a gate to a third input signal; and implementing a driver coupled to the node, the driver amplifying a voltage, adjusting logic levels, and providing an output signal, wherein each one of a plurality of paths to the output signal from the first input signal, the second input signal and the third input signal, respectively, has substantially equal delays, each one of the paths passing through the driver and one or more of the transmission gate and the pull transistor.
Claim 8
Dependent Claim
13 words
The method according to claim 6, wherein the map is a Karnaugh map.
Claim 9
Dependent Claim
20 words
The method according to claim 7, wherein the pairs of cells are pairs of adjacent cells in the Karnaugh map.
Claim 10
Dependent Claim
18 words
The method according to claim 6, wherein the transmission gate comprises an N-type transistor and a P-type transistor.
Claim 11
Dependent Claim
79 words
The method according to claim 6, wherein the step of adjusting electrical properties comprises the steps of: determining a ratio of N-type transistor size to P-type transistor size of a first transmission gate to ensure substantially equal rise and fall times of the transmission gate; and determining a ratio of the first transmission gate size to the first pull transistor size to ensure substantially equal rise and fall times of the first transmission gate and the first pull transistor.
Claim 12
Dependent Claim
79 words
The method according to claim 3, wherein the step of adjusting electrical properties comprises the steps of: determining a ratio of N-type transistor size to P-type transistor size of a first transmission gate to ensure substantially equal rise and fall times of the transmission gate; and determining a ratio of the first transmission gate size to the first pull transistor size to ensure substantially equal rise and fall times of the first transmission gate and the first pull transistor.
Claim 13
Dependent Claim
19 words
The method according to claim 11, further comprising the step of: providing a size for the first pull transistor.
Claim 14
Dependent Claim
19 words
The method according to claim 5, further comprising the step of: providing a size for the first pull transistor.
Claim 15
Dependent Claim
19 words
The method according to claim 10, further comprising the step of: providing a size for the first pull transistor.
Claim 16
Dependent Claim
24 words
The method according to claim 1, further comprising the step of: analyzing a circuit using a Directed Acyclic Graph (DAG) representation of the circuit.
Claim 17
Independent Claim
260 words
A method for designing a wave-pipelining circuit, the wave-pipelining circuit including a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern, the method comprising the steps: forming a map of the desired logic function; assigning cells of the map into pairs of cells; implementing a transmission gate for each one, if any, of the pairs of map cells that has one high value and one low value, and for each transmission gate, if any, coupling a first terminal to a first input signal, coupling a second terminal to a node, and coupling a gate to a second input signal; implementing a pull transistor for each one, if any, of the pairs of map cells having values that are equal, and for each pull transistor, if any, coupling a first terminal to a voltage source, coupling a second terminal to the node, and coupling a gate to a third input signal; implementing a driver coupled to the node, the driver amplifying a signal, adjusting logic levels, and providing an output signal; and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern for each one of a plurality of paths to the output signal from the first input signal, the second input signal and the third input signal, respectively, each one of the paths passing through the driver and one or more of the transmission gate and the pull transistor.
Claim 18
Independent Claim
260 words
A method for designing a wave-pipelining circuit, the wave-pipelining circuit including a field-effect transistor logic circuit that performs a desired logic function and that has a substantially uniform overall gate delay substantially independent of input transition pattern, the method comprising the steps: forming a map of the desired logic function; assigning cells of the map into pairs of cells; implementing a transmission gate for each one, if any, of the pairs of map cells that has one high value and one low value, and for each transmission gate, if any, coupling a first terminal to a first input signal, coupling a second terminal to a node, and coupling a gate to a second input signal; implementing a pull transistor for each one, if any, of the pairs of map cells having values that are equal, and for each pull transistor, if any, coupling a first terminal to a voltage source, coupling a second terminal to the node, and coupling a gate to a third input signal; implementing a driver coupled to the node, the driver amplifying a signal, adjusting logic levels, and providing an output signal; and adjusting electrical properties of the pull transistor and/or the transmission gate to provide the substantially uniform overall gate delay substantially independent of input transition pattern for each one of a plurality of paths to the output signal from the first input signal, the second input signal and the third input signal, respectively, each one of the paths passing through the driver and one or more of the transmission gate and the pull transistor.
Claim 19
Dependent Claim
13 words
The method according to claim 16, wherein the map is a Karnaugh map.
Claim 20
Dependent Claim
20 words
The method according to claim 17, wherein the pairs of cells are pairs of adjacent cells in the Karnaugh map.
Claim 21
Dependent Claim
40 words
The method according to claim 16, wherein the step of implementing a pull-up or a pull-down transistor includes the step of implementing a pull-up transistor if both values are high and implementing a pull-down transistor if both values are low.
Claim 22
Dependent Claim
18 words
The method according to claim 18, wherein the transmission gate comprises an N-type transistor and a P-type transistor.
Claim 23
Independent Claim
118 words
A method for designing a complementary field-effect transistor (FET) logic gate circuit having a delay substantially independent of input transition pattern for use in wave pipelining, the circuit having a first pull transistor having a first channel type, and a first transmission gate comprising an N-type FET and a P-type FET, the method comprising the steps: determining a ratio of N-type FET size to P-type FET size of the first transmission gate to ensure substantially equal rise and fall times of the first transmission gate; and determining a ratio of the first transmission gate size to the first pull transistor size to ensure substantially equal rise and fall times of the transmission gate and the first pull transistor.
Claim 24
Independent Claim
118 words
A method for designing a complementary field-effect transistor (FET) logic gate circuit having a delay substantially independent of input transition pattern for use in wave pipelining, the circuit having a first pull transistor having a first channel type, and a first transmission gate comprising an N-type FET and a P-type FET, the method comprising the steps: determining a ratio of N-type FET size to P-type FET size of the first transmission gate to ensure substantially equal rise and fall times of the first transmission gate; and determining a ratio of the first transmission gate size to the first pull transistor size to ensure substantially equal rise and fall times of the transmission gate and the first pull transistor.
Claim 25
Dependent Claim
71 words
The method according to claim 21, wherein the complementary FET logic gate circuit further comprises a second pull transistor having a channel type complementary to the first channel type of the first pull transistor, further comprising the step of: determining a ratio for the second pull transistor size to the first pull transistor size in order to ensure substantially equal rise and fall times of the first and second pull transistors.
Claim 26
Dependent Claim
19 words
The method according to claim 21, further comprising the step of: providing a size for the first pull transistor.
Claim 27
Dependent Claim
147 words
The method according to claim 21, wherein the complementary FET logic gate circuit further comprises a second pull transistor having a channel type complementary to the first channel type of the first pull transistor, and a second transmission gate comprising an N-type FET and a P-type FET, further comprising the steps of: determining a ratio of N-type FET size to P-type FET size of the second transmission gate to ensure substantially equal rise and fall times of the second transmission gate; determining a ratio of the second transmission gate size to the second pull transistor size to ensure substantially equal rise and fall times of the second transmission gate and the second pull transistor; and determining a ratio for the second pull transistor size to the first pull transistor size in order to ensure substantially equal rise and fall times of the first and second pull transistors.
Claim 28
Independent Claim
120 words
A system for designing a complementary field-effect transistor (FET) logic gate circuit having a delay substantially independent of input transition pattern for use in wave pipelining, the circuit having a first pull transistor having a first channel type, and a first transmission gate comprising an N-type FET and a P-type FET, the system comprising: means for determining a ratio of N-type FET size to P-type FET size of the first transmission gate to ensure substantially equal rise and fall times of the first transmission gate; and means for determining a ratio of the first transmission gate size to the first pull transistor size to ensure substantially equal rise and fall times of the transmission gate and the first pull transistor.
Claim 29
Independent Claim
120 words
A system for designing a complementary field-effect transistor (FET) logic gate circuit having a delay substantially independent of input transition pattern for use in wave pipelining, the circuit having a first pull transistor having a first channel type, and a first transmission gate comprising an N-type FET and a P-type FET, the system comprising: means for determining a ratio of N-type FET size to P-type FET size of the first transmission gate to ensure substantially equal rise and fall times of the first transmission gate; and means for determining a ratio of the first transmission gate size to the first pull transistor size to ensure substantially equal rise and fall times of the transmission gate and the first pull transistor.
Claim 30
Dependent Claim
51 words
The system according to claim 25, wherein the means for determining a ratio of N-type FET size to P-type FET size of the first transmission gate and the means for determining a ratio of the first transmission gate size to the first pull transistor size each include a SPICE circuit simulator.
Claim 31
Dependent Claim
150 words
The system according to claim 25, wherein the complementary FET logic gate circuit further comprises a second pull transistor having a channel type complementary to the first channel type of the first pull transistor, and a second transmission gate comprising an N-type FET and a P-type FET, further comprising: means for determining a ratio of N-type FET size to P-type FET size of the second transmission gate to ensure substantially equal rise and fall times of the second transmission gate; means for determining a ratio of the second transmission gate size to the second pull transistor size to ensure substantially equal rise and fall times of the second transmission gate and the second pull transistor; and means for determining a ratio for the second pull transistor size to the first pull transistor size in order to ensure substantially equal rise and fall times of the first and second pull transistors.
Claim 32
Dependent Claim
170 words
The system according to claim 25, wherein the complementary FET logic gate circuit further comprises a second transmission gate comprising an N-type FET and a P-type FET, and a third transmission gate comprising an N-type FET and a P-type FET, further comprising: means for determining a ratio of N-type FET size to P-type FET size of the second transmission gate to ensure substantially equal rise and fall times of the second transmission gate; means for determining a ratio of N-type FET size to P-type FET size of the second transmission gate to ensure substantially equal rise and fall times of the second transmission gate; means for determining a ratio of the second transmission gate size to the third transmission gate size to ensure substantially equal rise and fall times of the second and third transmission gates; means for determining a ratio for the second transmission gate size to the first transmission gate size in order to ensure substantially equal rise and fall times of the first and second transmission gates.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2001-08-17 | 2002-02-16 | 2002-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-17 | 2006-02-16 | 2006-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-17 | 2010-02-16 | 2010-08-18 | $7700.00 | Window Closed / Lapsed |