Complementary field-effect transistor logic circuits for wave pipelining

Claim 2

A logic circuit for performing a logic function, said logic circuit comprising: a first field-effect transistor having a first terminal coupled to a first input signal, a second terminal coupled to an internal node, and a gate coupled to a second input signal; a second field-effect transistor having a first terminal coupled to said first input signal, a second terminal coupled to said internal node, and a gate coupled to a logical complement of said second input signal; a third field-effect transistor having a first terminal coupled to a voltage source, a second terminal coupled to said internal node, and a gate coupled to said second input signal; and a driver coupled to said internal node, said driver comprising means for amplifying a voltage, adjusting logic levels, and providing an output signal, wherein each one of a plurality of paths to said output signal from said first input signal, said second input signal, and said logical complement of said second input signal, respectively, has substantially equal delays, each one of said paths passing through said driver and one or more of said first, second, and third field-effect transistors.

Claim 3

A logic circuit according to claim 1 wherein: said first field-effect transistor has a first channel type; said second field-effect transistor has a second channel type which is complementary to said first channel type; and said third field-effect transistor has said second channel type.

Claim 4

A logic circuit according to claim 2 wherein: said first channel type is an N-channel enhancement-mode channel; said second channel type is a P-channel enhancement-mode channel; and said voltage source is V DD .

Claim 5

A logic circuit according to claim 3 wherein: said logic function is a logical AND.

Claim 6

A logic circuit according to claim 3 wherein: said logic function is a logical NOR.

Claim 7

A logic circuit according to claim 2 wherein: said first channel type is a P-channel enhancement-mode channel; said second channel type is an N-channel enhancement-mode channel; and said voltage source is ground.

Claim 8

A logic circuit according to claim 6 wherein: said logic function is a logical NAND.

Claim 9

A logic circuit according to claim 6 wherein: said logic function is a logical OR.

Claim 10

A logic circuit comprising: a transmission gate having a first terminal coupled to a first input signal, a second terminal coupled to a node, and a gate coupled to a second input signal; a pull transistor having a first terminal coupled to a voltage source, a second terminal coupled to said node, and a gate coupled to a third input signal; and a driver coupled to said node, said driver comprising means for amplifying a voltage, adjusting logic levels, and providing an output signal said output signal, having substantially equivalent output transition times and substantially equivalent propagation delay times relative to any input signal transition.

Claim 11

A logic circuit comprising: a transmission gate having a first terminal coupled to a first input signal, a second terminal coupled to a node, and a gate coupled to a second input signal; a pull transistor having a first terminal coupled to a voltage source, a second terminal coupled to said node, and a gate coupled to a third input signal; and a driver coupled to said node, said driver comprising means for amplifying a voltage, adjusting logic levels, and providing an output signal said output signal, having substantially equivalent output transition times and substantially equivalent propagation delay times relative to any input signal transition.

Claim 12

A logic circuit according to claim 9 wherein said transmission gate comprises complementary field-effect transistors.

Claim 13

A logic circuit according to claim 10 wherein said complementary field-effect transistors comprise: at least one N-channel enhancement-mode transistor; and at least one P-channel enhancement-mode transistor.

Claim 14

A complementary field-effect transistor logic circuit comprising: a first pass transistor having a first channel type and having a first terminal coupled to a first input signal, a second terminal coupled to an internal node, and a gate coupled to a second input signal; a second pass transistor having a second channel type which is complementary to said first channel type and having a first terminal coupled to said first input signal, a second terminal coupled to said internal node, and a gate coupled to a logical complement of said second input signal; a third transistor having said second channel type and having a first terminal coupled to a voltage terminal, a second terminal coupled to said internal node, and a gate coupled to said second input signal; and a driver coupled to said internal node, comprising means for amplifying a voltage and adjusting logic levels at an output signal, said output signal having substantially equivalent output transition times and substantially equivalent propagation delay times relative to any input signal transition.

Claim 15

A complementary field-effect transistor logic circuit comprising: a first pass transistor having a first channel type and having a first terminal coupled to a first input signal, a second terminal coupled to an internal node, and a gate coupled to a second input signal; a second pass transistor having a second channel type which is complementary to said first channel type and having a first terminal coupled to said first input signal, a second terminal coupled to said internal node, and a gate coupled to a logical complement of said second input signal; a third transistor having said second channel type and having a first terminal coupled to a voltage terminal, a second terminal coupled to said internal node, and a gate coupled to said second input signal; and a driver coupled to said internal node, comprising means for amplifying a voltage and adjusting logic levels at an output signal, said output signal having substantially equivalent output transition times and substantially equivalent propagation delay times relative to any input signal transition.

Claim 16

A family of logic circuits for performing logic functions, said family comprising: a first logic circuit comprising: a first field-effect transistor having a first terminal coupled to a first input signal, a second terminal coupled to a first internal node, and a gate coupled to a second input signal; a second field-effect transistor having a first terminal coupled to said first input signal, a second terminal coupled to said first internal node, and a gate coupled to a logical complement of said second input signal; a third field-effect transistor having a first terminal coupled to a voltage source, a second terminal coupled to said first internal node, and a gate coupled to said second input signal; and a first driver coupled to said first internal node, said first driver comprising means for amplifying a voltage, adjusting logic levels, and providing a first output signal; a second logic circuit comprising: a first and a second transmission gate, wherein said first and second transmission gates have substantially equivalent output transition times and substantially equivalent propagation delay times, and wherein each of said first and second transmission gates comprise: a fourth field-effect transistor having a first terminal coupled to a third input signal, a second terminal coupled to a second internal node, and a gate coupled to a fourth input signal; and a fifth field-effect transistor having a first terminal coupled to said third input signal, a second terminal coupled to said second internal node, and a gate coupled to a logical complement of said fourth input signal; and a second driver coupled to said internal nodes of each of said first and second transmission gates, wherein said driver comprises means for amplifying a voltage, adjusting logic levels, and providing a second output signal; and wherein said first and second logic circuits have substantially equivalent output transition times and substantially equivalent propagation delay times.

Claim 17

A family of logic circuits for performing logic functions, said family comprising: a first logic circuit comprising: a first field-effect transistor having a first terminal coupled to a first input signal, a second terminal coupled to a first internal node, and a gate coupled to a second input signal; a second field-effect transistor having a first terminal coupled to said first input signal, a second terminal coupled to said first internal node, and a gate coupled to a logical complement of said second input signal; a third field-effect transistor having a first terminal coupled to a voltage source, a second terminal coupled to said first internal node, and a gate coupled to said second input signal; and a first driver coupled to said first internal node, said first driver comprising means for amplifying a voltage, adjusting logic levels, and providing a first output signal; a second logic circuit comprising: a first and a second transmission gate, wherein said first and second transmission gates have substantially equivalent output transition times and substantially equivalent propagation delay times, and wherein each of said first and second transmission gates comprise: a fourth field-effect transistor having a first terminal coupled to a third input signal, a second terminal coupled to a second internal node, and a gate coupled to a fourth input signal; and a fifth field-effect transistor having a first terminal coupled to said third input signal, a second terminal coupled to said second internal node, and a gate coupled to a logical complement of said fourth input signal; and a second driver coupled to said internal nodes of each of said first and second transmission gates, wherein said driver comprises means for amplifying a voltage, adjusting logic levels, and providing a second output signal; and wherein said first and second logic circuits have substantially equivalent output transition times and substantially equivalent propagation delay times.

Claim 18

A logic circuit for performing a wave-pipelined logic function, said logic circuit comprising: a first, second, third, and fourth logic circuit, each of said logic circuits comprising: a first field-effect transistor (FET) having a first terminal coupled to a first input signal, a second terminal coupled to a first internal node, and a gate coupled to a second input signal; a second FET having a first terminal coupled to said first input signal, a second terminal coupled to said first internal node, and a gate coupled to a logical complement of said second input signal; a third FET having a first terminal coupled to a voltage source, a second terminal coupled to said first internal node, and a gate coupled to said second input signal; and a driver coupled to said first internal node, said driver comprising means for amplifying a voltage, adjusting logic levels, and providing a first output signal; said first and second logic circuits forming a first stage and said third and fourth logic circuits forming a second stage, said output of said first logic circuit being coupled as said second input signal for said third logic circuit, said output of said second logic circuit being coupled as said logical complement of second input signal for said third logic circuit, said first FET of said first and third logic circuits and said second and third FETs of said second and fourth logic circuits each having a first channel type, said first FET of said second and fourth logic circuits and said second and third FETs of said first and third logic circuits each having a second channel type, and said first, second, third, and fourth logic circuits having substantially equivalent output transition times and substantially equivalent propagation delay times.

Claim 19

A logic circuit for performing a wave-pipelined logic function, said logic circuit comprising: a first, second, third, and fourth logic circuit, each of said logic circuits comprising: a first field-effect transistor (FET) having a first terminal coupled to a first input signal, a second terminal coupled to a first internal node, and a gate coupled to a second input signal; a second FET having a first terminal coupled to said first input signal, a second terminal coupled to said first internal node, and a gate coupled to a logical complement of said second input signal; a third FET having a first terminal coupled to a voltage source, a second terminal coupled to said first internal node, and a gate coupled to said second input signal; and a driver coupled to said first internal node, said driver comprising means for amplifying a voltage, adjusting logic levels, and providing a first output signal; said first and second logic circuits forming a first stage and said third and fourth logic circuits forming a second stage, said output of said first logic circuit being coupled as said second input signal for said third logic circuit, said output of said second logic circuit being coupled as said logical complement of second input signal for said third logic circuit, said first FET of said first and third logic circuits and said second and third FETs of said second and fourth logic circuits each having a first channel type, said first FET of said second and fourth logic circuits and said second and third FETs of said first and third logic circuits each having a second channel type, and said first, second, third, and fourth logic circuits having substantially equivalent output transition times and substantially equivalent propagation delay times.

Claim 20

A logic circuit for performing a logic function which generates a result, the result having both a first output signal and a second output signal, the second output signal being a logical complement of the first output signal, both output signals having substantially equivalent output transition times and substantially equivalent propagation delay times relative to any input signal transition, the circuit comprising: a first field-effect transistor having a first terminal coupled to a first input signal, a second terminal coupled to a first internal node, and a gate coupled to a second input signal; a second field-effect transistor having a first terminal coupled to the first input signal, a second terminal coupled to the first internal node, and a gate coupled to a logical complement of the second input signal; a third field-effect transistor having a first terminal coupled to a first voltage source, a second terminal coupled to the first internal node, and a gate coupled to the logical complement of the second input signal; a first driver coupled to the first internal node, the first driver comprising means for amplifying a voltage, adjusting logic levels, and providing the first output signal; a fourth field-effect transistor having a first terminal coupled to a logical complement of the first input signal, a second terminal coupled to a second internal node, and a gate coupled to the second input signal; a fifth field-effect transistor having a first terminal coupled to the logical complement of the first input signal, a second terminal coupled to the second internal node, and a gate coupled to the logical complement of the second input signal; a sixth field-effect transistor having a first terminal coupled to a second voltage source, a second terminal coupled to the second internal node, and a gate coupled to the second input signal; and a second driver coupled to the second internal node, the second driver comprising means for amplifying a voltage, adjusting logic levels, and providing the second output signal.

Claim 21

A logic circuit for performing a logic function which generates a result, the result having both a first output signal and a second output signal, the second output signal being a logical complement of the first output signal, both output signals having substantially equivalent output transition times and substantially equivalent propagation delay times relative to any input signal transition, the circuit comprising: a first field-effect transistor having a first terminal coupled to a first input signal, a second terminal coupled to a first internal node, and a gate coupled to a second input signal; a second field-effect transistor having a first terminal coupled to the first input signal, a second terminal coupled to the first internal node, and a gate coupled to a logical complement of the second input signal; a third field-effect transistor having a first terminal coupled to a first voltage source, a second terminal coupled to the first internal node, and a gate coupled to the logical complement of the second input signal; a first driver coupled to the first internal node, the first driver comprising means for amplifying a voltage, adjusting logic levels, and providing the first output signal; a fourth field-effect transistor having a first terminal coupled to a logical complement of the first input signal, a second terminal coupled to a second internal node, and a gate coupled to the second input signal; a fifth field-effect transistor having a first terminal coupled to the logical complement of the first input signal, a second terminal coupled to the second internal node, and a gate coupled to the logical complement of the second input signal; a sixth field-effect transistor having a first terminal coupled to a second voltage source, a second terminal coupled to the second internal node, and a gate coupled to the second input signal; and a second driver coupled to the second internal node, the second driver comprising means for amplifying a voltage, adjusting logic levels, and providing the second output signal.