US5796137A
Expired / Lapsed
US
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Semiconductor memory device having capacitor of thin film transistor structure
Assignee: Toshiba Corp
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Filing: 1996-08-09
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Granted: 1998-08-18
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Expires: 2016-08-09
Abstract
Abstract The gate of a selection transistor is connected to a word line and the source thereof is connected to a bit line. The drain of the selection transistor is connected to a storage node constituting a capacitor of thin film transistor structure. The capacitor has a plate electrode insulated from the storage node, that portion of the plate electrode which is disposed in opposition to the storage node is formed to have an impurity concentration lower than the remaining portion thereof and an inverted layer is formed in the corresponding portion according to data stored in the storage node. The plate electrode is connected to pulse generation means, a pulse signal is output from the pulse generation means in the data readout operation and the potential of the plate electrode is raised by the pulse signal.
Inventors
- 👤 Kiyofumi Ochii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 06:24
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4074; G11C11/403; G11C11/404; H; H10; H10B; H10B12/00
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
134 words
A semiconductor memory device having a word line and a bit line, the semiconductor memory device comprising: a selection transistor having a gate coupled to the word line and a current path having a first end coupled to the bit line, and a second end; a capacitor having a storage node coupled to the second end of the current path and a plate electrode insulated from said storage node, a portion of said plate electrode in opposition to the storage node having an impurity concentration lower than a remaining portion thereof and serving as a channel region, the plate electrode having no direct electrical connection with the second end; pulse generation means for supplying a pulse to said plate electrode; and means, operative during an occurrence of the pulse, for enabling the word line.
Claim 2
Dependent Claim
134 words
A semiconductor memory device having a word line and a bit line, the semiconductor memory device comprising: a selection transistor having a gate coupled to the word line and a current path having a first end coupled to the bit line, and a second end; a capacitor having a storage node coupled to the second end of the current path and a plate electrode insulated from said storage node, a portion of said plate electrode in opposition to the storage node having an impurity concentration lower than a remaining portion thereof and serving as a channel region, the plate electrode having no direct electrical connection with the second end; pulse generation means for supplying a pulse to said plate electrode; and means, operative during an occurrence of the pulse, for enabling the word line.
Claim 3
Dependent Claim
24 words
A device according to claim 1, wherein said capacitor includes a thin film structure in which said storage node serves as a gate electrode.
Claim 4
Dependent Claim
15 words
A device according to claim 2, wherein said storage node and plate electrode include polysilicon.
Claim 5
Dependent Claim
16 words
A device according to claim 2, wherein said storage node and plate electrode include amorphous silicon.
Claim 6
Dependent Claim
17 words
A device according to claim 2, wherein said storage node and plate electrode include single crystal silicon.
Claim 7
Dependent Claim
82 words
A device according to claim 1, wherein said pulse generation means includes an oscillation circuit for generating the pulse; a booster circuit for raising the pulse generated from said oscillation circuit to a preset potential; and a supply circuit for supplying the preset potential pulse output from said booster circuit to said plate electrode before selection of said selection transistor in a readout operation and interrupting supply of the pulse to said plate electrode before selection of said selection transistor is terminated.
Claim 8
Dependent Claim
134 words
A semiconductor memory device having a word line and a bit line, the semiconductor memory device comprising: a selection transistor having a gate coupled to the word line and a current path having a first end coupled the bit line, and a second end; a capacitor having a storage node coupled to the second end of the current path and a plate electrode insulated from said storage node, a portion of said plate electrode in opposition to said storage node having an impurity concentration lower than a remaining portion thereof and serving as a channel region, the plate electrode having no direct electrical connection with the second end; selection signal creation means for creating a selection signal for selecting said word line; and supplying means for supplying a pulse signal to said plate electrode.
Claim 9
Dependent Claim
134 words
A semiconductor memory device having a word line and a bit line, the semiconductor memory device comprising: a selection transistor having a gate coupled to the word line and a current path having a first end coupled the bit line, and a second end; a capacitor having a storage node coupled to the second end of the current path and a plate electrode insulated from said storage node, a portion of said plate electrode in opposition to said storage node having an impurity concentration lower than a remaining portion thereof and serving as a channel region, the plate electrode having no direct electrical connection with the second end; selection signal creation means for creating a selection signal for selecting said word line; and supplying means for supplying a pulse signal to said plate electrode.
Claim 10
Dependent Claim
14 words
A device according to claim 7, wherein said supplying means includes an AND circuit.
Claim 11
Dependent Claim
135 words
A semiconductor memory device having a word line and a bit line, the semiconductor memory device comprising: a selection transistor having a gate coupled to the word line and a current path having a first end coupled the bit line, and a second end; a capacitor having a node for storing data, coupled to the second end of the current path, and a plate electrode insulated from said storage node, a portion of said plate electrode being in opposition to said storage node and having a resistance that differs from that of the remainder of said plate electrode and that changes in accordance with the data; means for creating a pulse signal; means for creating a selection signal for selecting said word line; and supplying means for supplying the pulse signal to said plate electrode.
Claim 12
Dependent Claim
135 words
A semiconductor memory device having a word line and a bit line, the semiconductor memory device comprising: a selection transistor having a gate coupled to the word line and a current path having a first end coupled the bit line, and a second end; a capacitor having a node for storing data, coupled to the second end of the current path, and a plate electrode insulated from said storage node, a portion of said plate electrode being in opposition to said storage node and having a resistance that differs from that of the remainder of said plate electrode and that changes in accordance with the data; means for creating a pulse signal; means for creating a selection signal for selecting said word line; and supplying means for supplying the pulse signal to said plate electrode.
Claim 13
Dependent Claim
34 words
A device according to claim 9, wherein said supplying means includes an AND circuit including a first input responsive to the pulse signal; a second input responsive to the selection signal; and an output.
References Cited (Backward Citations)
US4584670A
Cited
US4786954A
Cited
US4849801A
Cited
US4799193A
Cited
US4845673A
Cited
US4855801A
Cited
EP0329569A2
Cited
JPH021155A
Cited
US5214304A
Cited
JPH0266967A
Cited
US5070385A
Cited
US5563434A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-17 | 2002-02-16 | 2002-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-17 | 2006-02-16 | 2006-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-17 | 2010-02-16 | 2010-08-18 | $7700.00 | Window Closed / Lapsed |