US4845673A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic memory with single-cycle writing of a field of logic states
Assignee: STMicroelectronics SA
•
Filing: 1987-02-09
•
Granted: 1989-07-04
•
Expires: 2007-02-09
Abstract
Abstract The present invention pertains to a dynamic memory. The voltage of the hot spot of the storage capacitor is carried to a value such that all the cells comprise the same logic value, owing to a potential generator. It is thus possible to write and read bit fields on a large-capacity memory at high speed. This device has applications with respect to image memories and for manufacturing tests.
Inventors
- 👤 Christophe Chevalier
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:50
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4072; G11C11/4074
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
206 words
A dynamic RAM memory comprising: an array of memory cells, with each cell comprising a series arrangement of a transistor and a storage capacitor, said capacitor of each cell having a first plate connected to the transistor of the corresponding cell and a second plate, wherein each of said cells is capable of storing either a first quantity of charge corresponding to a first programming state or a second quantity of charge corresponding to a second programming state, wherein the second plate of the capacitor of the cells forming the array are connected to a common potential generator capable of being switched to supply either a first potential or a second potential; wherein said first potential is used during the individual reading or writing step of information of a given cell, with said potential generator being controlled so that in a single writing action of all cells, while the cells are not individually addressed, said generator first supplies said second potential to the second plates of said cells, in order to set in a conduction state of the transistors of each of the cells in said first state, thereby charging the capacitors of said cells to said second state, and then secondly supplying said first potential.
Claim 2
Dependent Claim
206 words
A dynamic RAM memory comprising: an array of memory cells, with each cell comprising a series arrangement of a transistor and a storage capacitor, said capacitor of each cell having a first plate connected to the transistor of the corresponding cell and a second plate, wherein each of said cells is capable of storing either a first quantity of charge corresponding to a first programming state or a second quantity of charge corresponding to a second programming state, wherein the second plate of the capacitor of the cells forming the array are connected to a common potential generator capable of being switched to supply either a first potential or a second potential; wherein said first potential is used during the individual reading or writing step of information of a given cell, with said potential generator being controlled so that in a single writing action of all cells, while the cells are not individually addressed, said generator first supplies said second potential to the second plates of said cells, in order to set in a conduction state of the transistors of each of the cells in said first state, thereby charging the capacitors of said cells to said second state, and then secondly supplying said first potential.
Claim 3
Dependent Claim
81 words
A dynamic memory cell according to claim 1, wherein means are provided for writing binary data in the cells of the array, said data being either a logic zero or a logic one, said logic zero and logic one each corresponding to one of said states of the cells, and further comprising: logic means capable of being controlled for inverting when desired the binary data prior to their application to the cells and means for inverting data read from the cells.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-03 | 1993-01-02 | 1993-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-03 | 1997-01-02 | 1997-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-03 | 2001-01-02 | 2001-07-04 | $7700.00 | Window Closed / Lapsed |