EP0144710A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Circuit for applying a voltage to a memory cell mos capacitor of a semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1984-10-30
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Granted: —
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Expires: 2004-10-30
Abstract
Abstract A voltage applying circuit (b) is adapted to a semiconductor memory device comprising a plurality of memory cells (1) which each include MOS memory capacitors (3) one terminal of each being connected to a common point. The output terminal of said voltage applying circuit is connected to the common point of the MOS capacitor (3), and a low voltage for normal operation of the MOS capacitor (3) and a screening voltage for distinguishing a memory device, which is higher than that voltage, are selectively applied to the common connection point.
Inventors
- 👤 Mitsugi C/O Patent Division Ogura
- 👤 Fujio C/O Patent Division Masuoka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 16:24
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/4074; G11C29/00; G11C29/04; G11C29/50
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
95 words
A voltage applying circuit (6) adapted to a semiconductor memory device comprising a plurality of memory cells (1) which each include a MOS memory capacitor (3), one terminal of each being connected to a common point, and characterized in that the output terminal of said voltage applying circuit (6) is connected to said common point of said MOS capacitor (3), and a low voltage for normal operation of said MOS capacitor (3) and a screening voltage for distinguishing a memory device, which is higher than said voltage, are selectively applied to said common connection point.
Claim 2
Dependent Claim
95 words
A voltage applying circuit (6) adapted to a semiconductor memory device comprising a plurality of memory cells (1) which each include a MOS memory capacitor (3), one terminal of each being connected to a common point, and characterized in that the output terminal of said voltage applying circuit (6) is connected to said common point of said MOS capacitor (3), and a low voltage for normal operation of said MOS capacitor (3) and a screening voltage for distinguishing a memory device, which is higher than said voltage, are selectively applied to said common connection point.
Claim 3
Dependent Claim
38 words
A voltage applying circuit according to claim 1, characterized in that the normal operation voltage of said memory cell (1) is substantially 1/2 the power source voltage Vcc and said screening voltage is the power source voltage Vcc.
Claim 4
Dependent Claim
32 words
A voltage applying circuit according to claim 1, characterized in that the normal operation voltage of said memory cell (1) is the ground potential and said MOS capacitor is a depletion type.
References Cited (Backward Citations)
No citation records indexed.
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