US4491936A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic random access memory cell with increased signal margin
Assignee: STMicroelectronics lnc USA
•
Filing: 1982-02-08
•
Granted: 1985-01-01
•
Expires: 2002-02-08
Abstract
Abstract A dynamic random access memory cell (30) includes an access transistor (32) having the gate terminal thereof connected to a word line (34) and the source and drain terminals thereof connected between a bit line (36) and a node (37). A charge storage capacitor (38) is connected between the node (37) and a decoded plate line (40). The plate line (40) receives a bi-level voltage which shifts levels in a timing sequence keyed to the word line (34) signal. Shifting of voltage levels provided to the capacitor (38) through the plate line (40) essentially doubles the signal margin of the memory circuit (30) to thereby enhance the reliability of the data stored in the memory circuit (30).
Inventors
- 👤 Sargent S. Eaton, Jr.
- 👤 Robert J. Proebsting
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 16:11
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
198 words
A method of operation for a dynamic semiconductor memory cell, comprising the steps of: floating a bit line at a predetermined voltage state; driving a selected word line from a first voltage state to a second voltage state, said word line connected to the gate terminal of an access transistor; driving a selected plate line from said second voltage state to said first voltage state prior to the time of driving said selected word line from a first voltage state to a high voltage state, said plate line connected to a first terminal of a capacitor, the drain and source terminals of said transistor connected between said bit line and a second terminal of said capacitor; sensing the voltage level on said bit line after word line has been driven to said second voltage state and said plate line has been driven to said first voltage state; driving said plate line from said first voltage state to said second voltage state after said step of sensing; and driving said word line from said second voltage state to said first voltage state after said plate line has been driven from said first voltage state to said second voltage state.
Claim 2
Independent Claim
198 words
A method of operation for a dynamic semiconductor memory cell, comprising the steps of: floating a bit line at a predetermined voltage state; driving a selected word line from a first voltage state to a second voltage state, said word line connected to the gate terminal of an access transistor; driving a selected plate line from said second voltage state to said first voltage state prior to the time of driving said selected word line from a first voltage state to a high voltage state, said plate line connected to a first terminal of a capacitor, the drain and source terminals of said transistor connected between said bit line and a second terminal of said capacitor; sensing the voltage level on said bit line after word line has been driven to said second voltage state and said plate line has been driven to said first voltage state; driving said plate line from said first voltage state to said second voltage state after said step of sensing; and driving said word line from said second voltage state to said first voltage state after said plate line has been driven from said first voltage state to said second voltage state.
Claim 3
Independent Claim
196 words
A method of operation for a dynamic semiconductor memory cell, comprising the steps of: floating a bit line at a predetermined voltage state; driving a selected word line from a low voltage state to a high voltage state, said word line connected to the gate terminal of an access transistor having a first terminal thereof connected to said bit line; driving a selected plate line from said high voltage state to said low voltage state prior to the time of driving said selected word line from a low voltage state to a high voltage state, said plate line connected to a first terminal of a capacitor having a second terminal thereof connected to a second terminal of said access transistor; sensing the charge transferred from said capacitor to said bit line when said word line is at said high voltage state and said plate line is at said low voltage state; driving said plate line from said low voltage state to said high voltage state after said step of sensing; and driving said word line from said high voltage state to said low voltage state after said plate line is driven to said high voltage state.
Claim 4
Independent Claim
196 words
A method of operation for a dynamic semiconductor memory cell, comprising the steps of: floating a bit line at a predetermined voltage state; driving a selected word line from a low voltage state to a high voltage state, said word line connected to the gate terminal of an access transistor having a first terminal thereof connected to said bit line; driving a selected plate line from said high voltage state to said low voltage state prior to the time of driving said selected word line from a low voltage state to a high voltage state, said plate line connected to a first terminal of a capacitor having a second terminal thereof connected to a second terminal of said access transistor; sensing the charge transferred from said capacitor to said bit line when said word line is at said high voltage state and said plate line is at said low voltage state; driving said plate line from said low voltage state to said high voltage state after said step of sensing; and driving said word line from said high voltage state to said low voltage state after said plate line is driven to said high voltage state.
References Cited (Backward Citations)
US4409672A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-01-01 | 1988-07-02 | 1989-01-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-01-01 | 1992-07-02 | 1993-01-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-01-01 | 1996-07-02 | 1997-01-01 | $7700.00 | Window Closed / Lapsed |