Semiconductor memory device having capacitor of thin film transistor structure

Claim 2

A semiconductor memory device having a word line and a bit line, the semiconductor memory device comprising: a selection transistor having a gate coupled to the word line and a current path having a first end coupled to the bit line, and a second end; a capacitor having a node for storing data, coupled to the second end of the current path, and a plate electrode, a portion of said plate electrode in opposition to the node having an impurity concentration lower than a remaining portion thereof and serving as a channel region, the plate electrode having no direct electrical connection with the second end, wherein said channel region is rendered conductive when data stored in said node is set at one of two logic levels; and pulse generation means for selectively changing a potential of the channel region depending on a potential on the node and for supplying a pulse to said plate electrode during a node readout operation.

Claim 3

The semiconductor memory device according to claim 1, wherein said capacitor includes a thin film transistor structure in which said storage node serves as a gate electrode.

Claim 4

A device according to claim 2, wherein said storage node and plate electrode include polysilicon.

Claim 5

A device according to claim 2, wherein said storage node and plate electrode include amorphous silicon.

Claim 6

A device according to claim 2, wherein said storage node and plate electrode include single crystal silicon.

Claim 7

A semiconductor memory device having a word line and a bit line, the semiconductor memory device comprising: a selection transistor having a gate coupled to the word line and a current path having a first end coupled to the bit line, and a second end; a capacitor having a storage node for storing data, coupled to the second end of the current path, and a plate electrode, a portion of said plate electrode in opposition to the storage node having an impurity concentration lower than a remaining portion thereof and serving as a channel region, the plate electrode having no direct electrical connection with the second end, wherein an inverted layer is formed in the portion of the plate electrode when data stored in said storage node is set at one of two logic-levels; means for selectively changing a potential of the portion of said plate electrode depending on a potential on the storage node; the changing means including an oscillation circuit for generating a pulse signal, a booster circuit for raising a pulse signal generated from said oscillation circuit to a preset potential, and a supply circuit for supplying the preset potential from said booster circuit to said plate electrode before selection of said selection transistor in a readout operation and interrupting supply of the potential to said plate electrode before selection of said selection transistor is terminated.

Claim 8

A semiconductor memory device having a word line and a bit line, the semiconductor memory device comprising: a selection transistor having a gate coupled to the word line and a current path having a first end coupled to the bit line, and a second end; a capacitor having a storage node for storing data, coupled to the second end of the current path, and a plate electrode, a portion of said plate electrode in opposition to the storage node having an impurity concentration lower than a remaining portion thereof and serving as a channel region, the plate electrode having no direct electrical connection with the second end, wherein an inverted layer is formed in the portion of the plate electrode when data stored in said storage node is set at one of two logic-levels; means for selectively changing a potential of the portion of said plate electrode depending on a potential on the storage node; the changing means including an oscillation circuit for generating a pulse signal, a booster circuit for raising a pulse signal generated from said oscillation circuit to a preset potential, and a supply circuit for supplying the preset potential from said booster circuit to said plate electrode before selection of said selection transistor in a readout operation and interrupting supply of the potential to said plate electrode before selection of said selection transistor is terminated.

Claim 9

A semiconductor memory device having a word line and a bit line, the semiconductor memory device comprising: a selection transistor having a gate coupled to the word line and a circuit path having a first end coupled to the bit line, and a second end; a capacitor having a storage node coupled to the second end of the current path and a plate electrode, a portion of said plate electrode in opposition to the storage node having an impurity concentration lower than a remaining portion thereof and serving as a channel region, the plate electrode having no direct electrical connection with the second end, wherein said channel region is rendered conductive when data stored in said node is set at one of two logic-levels; means for generating a pulse signal; and means for selectively changing a potential of the portion of said plate electrode depending on a potential on the storage node, the changing means including means for supplying the pulse signal to the plate electrode when reading out the stored data.

Claim 10

A semiconductor memory device having a word line and a bit line, the semiconductor memory device comprising: a selection transistor having a gate coupled to the word line and a circuit path having a first end coupled to the bit line, and a second end; a capacitor having a storage node coupled to the second end of the current path and a plate electrode, a portion of said plate electrode in opposition to the storage node having an impurity concentration lower than a remaining portion thereof and serving as a channel region, the plate electrode having no direct electrical connection with the second end, wherein said channel region is rendered conductive when data stored in said node is set at one of two logic-levels; means for generating a pulse signal; and means for selectively changing a potential of the portion of said plate electrode depending on a potential on the storage node, the changing means including means for supplying the pulse signal to the plate electrode when reading out the stored data.

Claim 11

A semiconductor memory device having a word line and a bit line, the semiconductor memory device comprising: a semiconductor substrate; a MOS type selection transistor having diffused layers defining source and drain regions in said semiconductor substrate and a gate electrode defining a word line over said semiconductor substrate; a first semiconductor layer defining a storage node on a first one of said diffused layers of said selection transistor, said first semiconductor layer having a first area; a second semiconductor layer over said first semiconductor layer and having an area larger than said first area, a first portion in opposition to said first semiconductor layer, and a remaining portion, the first portion including an impurity concentration lower than the remaining portion, the remaining portion including a plate electrode of relatively high impurity concentration, the plate electrode having no direct electrical connection with the first one of said diffused layers, wherein an inverted layer is formed in said first portion when data stored in said storage node is set at one of two logic-levels; and means for selectively changing a potential of said first portion, during a storage node readout operation, depending on a potential on the storage node.

Claim 12

A semiconductor memory device having a word line and a bit line, the semiconductor memory device comprising: a semiconductor substrate; a MOS type selection transistor having diffused layers defining source and drain regions in said semiconductor substrate and a gate electrode defining a word line over said semiconductor substrate; a first semiconductor layer defining a storage node on a first one of said diffused layers of said selection transistor, said first semiconductor layer having a first area; a second semiconductor layer over said first semiconductor layer and having an area larger than said first area, a first portion in opposition to said first semiconductor layer, and a remaining portion, the first portion including an impurity concentration lower than the remaining portion, the remaining portion including a plate electrode of relatively high impurity concentration, the plate electrode having no direct electrical connection with the first one of said diffused layers, wherein an inverted layer is formed in said first portion when data stored in said storage node is set at one of two logic-levels; and means for selectively changing a potential of said first portion, during a storage node readout operation, depending on a potential on the storage node.

Claim 13

A device according to claim 8, wherein said first and second semiconductor layers include polysilicon.

Claim 14

A device according to claim 8, wherein said second semiconductor layer includes amorphous silicon.

Claim 15

A device according to claim 8, wherein said first and second semiconductor layers include single crystal silicon.

Claim 16

A semiconductor memory device having a word line and a bit line, the semiconductor memory device comprising: a selection transistor having a gate coupled to the word line and a current path having a first end coupled to the bit line, and a second end; a capacitor having a node for storing data, coupled to the second end of the current path, and a plate electrode, a portion of said plate electrode being in opposition to the node and having an impurity concentration lower than a remaining portion thereof, wherein an inverted layer is formed in the portion of said plate electrode when data stored in said storage node is set at one of two logic-levels; and means for selectively changing a potential of the portion of said plate electrode, during a node readout operation, depending on a potential on the node, including an oscillation circuit for generating a pulse signal, a booster circuit for raising a pulse signal generated from said oscillation circuit to a preset potential, and a supply circuit for supplying the preset potential from said booster circuit to said plate electrode before selection of said selection transistor in a readout operation and interrupting supply of the potential to said plate electrode before selection of said selection transistor is terminated.

Claim 17

A semiconductor memory device having a word line and a bit line, the semiconductor memory device comprising: a selection transistor having a gate coupled to the word line and a current path having a first end coupled to the bit line, and a second end; a capacitor having a node for storing data, coupled to the second end of the current path, and a plate electrode, a portion of said plate electrode being in opposition to the node and having an impurity concentration lower than a remaining portion thereof, wherein an inverted layer is formed in the portion of said plate electrode when data stored in said storage node is set at one of two logic-levels; and means for selectively changing a potential of the portion of said plate electrode, during a node readout operation, depending on a potential on the node, including an oscillation circuit for generating a pulse signal, a booster circuit for raising a pulse signal generated from said oscillation circuit to a preset potential, and a supply circuit for supplying the preset potential from said booster circuit to said plate electrode before selection of said selection transistor in a readout operation and interrupting supply of the potential to said plate electrode before selection of said selection transistor is terminated.