Method of fabricating a stack/trench capacitor for a dynamic random access memory (DRAM)

Claim 1

A method for fabricating an array of memory cells, comprising the steps of: providing a silicon substrate; forming a gate oxide layer on device areas for field effect transistors; depositing a first polysilicon layer on the device areas and patterning the first polysilicon layer to form gate electrodes for the field effect transistors; forming source/drain areas adjacent to the gate electrodes; and forming an array of stacked capacitors by: depositing a first insulating layer on the patterned first polysilicon layer, and elsewhere on the substrate, masking and anisotropically etching contact openings in the first insulating layer to storage node junction areas in the source/drain contact areas, depositing a second polysilicon layer, depositing a first spacer layer on the second polysilicon layer, depositing a second spacer layer on the first spacer layer, patterning the first and second spacer layers by masking and anisotropic etching to leave portions on the second polysilicon layer, isotropically etching the first spacer layer and thereby recessing the first spacer layer under the second spacer layer, depositing a third polysilicon layer on the second and in the recesses on the first spacer layers, and elsewhere on the second polysilicon layer, anisotropically etching back the third polysilicon layer to the third insulating layer, and etching further using the patterned third insulating layer as an etch mask, etching the second polysilicon layer to form bottom electrodes for the stacked capacitors with vertical portions in the recesses, etching remaining portions of the first and second spacer layers to expose more of the bottom electrodes, forming an interelectrode insulator on the bottom electrodes, depositing and patterning a conductive layer on the interelectrode insulator, forming top electrodes, and completing the array of stacked capacitors.

Claim 2

A method for fabricating an array of memory cells, comprising the steps of: providing a silicon substrate; forming a gate oxide layer on device areas for field effect transistors; depositing a first polysilicon layer on the device areas and patterning the first polysilicon layer to form gate electrodes for the field effect transistors; forming source/drain areas adjacent to the gate electrodes; and forming an array of stacked capacitors by: depositing a first insulating layer on the patterned first polysilicon layer, and elsewhere on the substrate, masking and anisotropically etching contact openings in the first insulating layer to storage node junction areas in the source/drain contact areas, depositing a second polysilicon layer, depositing a first spacer layer on the second polysilicon layer, depositing a second spacer layer on the first spacer layer, patterning the first and second spacer layers by masking and anisotropic etching to leave portions on the second polysilicon layer, isotropically etching the first spacer layer and thereby recessing the first spacer layer under the second spacer layer, depositing a third polysilicon layer on the second and in the recesses on the first spacer layers, and elsewhere on the second polysilicon layer, anisotropically etching back the third polysilicon layer to the third insulating layer, and etching further using the patterned third insulating layer as an etch mask, etching the second polysilicon layer to form bottom electrodes for the stacked capacitors with vertical portions in the recesses, etching remaining portions of the first and second spacer layers to expose more of the bottom electrodes, forming an interelectrode insulator on the bottom electrodes, depositing and patterning a conductive layer on the interelectrode insulator, forming top electrodes, and completing the array of stacked capacitors.

Claim 13

A method for fabricating an array of dynamic random access memory cells having trench/stacked capacitors on a silicon substrate, comprising the steps of: providing a silicon substrate; forming field oxide regions on the silicon substrate around and electrically isolating an array of device areas for field effect transistors; forming a gate oxide layer on the device areas; depositing a first polysilicon layer on the device and field oxide areas; patterning the first polysilicon layer forming gate electrodes on the device areas for the field effect transistors and also electrically conducting portions on the field oxide areas for word lines; forming source/drain areas adjacent to the gate electrodes; and forming an array of capacitors by: depositing a first insulating layer on the patterned first polysilicon layer, masking and anisotropically etching contact openings in the first insulating layer to storage node junction areas in the source/drain contact areas, and further forming trenches in the silicon substrate, depositing a doped second polysilicon layer on the first insulating layer and in the trenches, the doped second polysilicon layer also contacting in the trenches the source/drain contact areas, depositing a second insulating layer on the second polysilicon layer, depositing a third insulating layer composed of silicon nitride on the second insulating layer, patterning the second and third insulating layers by masking and anisotropic etching leaving portions on the second polysilicon layer aligned over the trenches, isotropically and selectively etching the second insulating layer and thereby recessing the second insulating layer under the patterned third insulating layer, depositing a third polysilicon layer on the patterned second and third insulating layers, anisotropically etching back the third polysilicon layer to the third insulating layer, and further using the patterned third insulating layer as a mask, patterning the second polysilicon layer and thereby forming an array of electrically isolated bottom electrodes for the stacked capacitors with vertical portions in the recesses, and contiguous with the second polysilicon layer in the trenches, removing by isotropic wet etching remaining portions of the second and third insulating layers, forming an interelectrode insulator on the bottom electrodes, forming top electrodes, and completing the array of dynamic random access memory cells having capacitors.

Claim 14

A method for fabricating an array of dynamic random access memory cells having trench/stacked capacitors on a silicon substrate, comprising the steps of: providing a silicon substrate; forming field oxide regions on the silicon substrate around and electrically isolating an array of device areas for field effect transistors; forming a gate oxide layer on the device areas; depositing a first polysilicon layer on the device and field oxide areas; patterning the first polysilicon layer forming gate electrodes on the device areas for the field effect transistors and also electrically conducting portions on the field oxide areas for word lines; forming source/drain areas adjacent to the gate electrodes; and forming an array of capacitors by: depositing a first insulating layer on the patterned first polysilicon layer, masking and anisotropically etching contact openings in the first insulating layer to storage node junction areas in the source/drain contact areas, and further forming trenches in the silicon substrate, depositing a doped second polysilicon layer on the first insulating layer and in the trenches, the doped second polysilicon layer also contacting in the trenches the source/drain contact areas, depositing a second insulating layer on the second polysilicon layer, depositing a third insulating layer composed of silicon nitride on the second insulating layer, patterning the second and third insulating layers by masking and anisotropic etching leaving portions on the second polysilicon layer aligned over the trenches, isotropically and selectively etching the second insulating layer and thereby recessing the second insulating layer under the patterned third insulating layer, depositing a third polysilicon layer on the patterned second and third insulating layers, anisotropically etching back the third polysilicon layer to the third insulating layer, and further using the patterned third insulating layer as a mask, patterning the second polysilicon layer and thereby forming an array of electrically isolated bottom electrodes for the stacked capacitors with vertical portions in the recesses, and contiguous with the second polysilicon layer in the trenches, removing by isotropic wet etching remaining portions of the second and third insulating layers, forming an interelectrode insulator on the bottom electrodes, forming top electrodes, and completing the array of dynamic random access memory cells having capacitors.