US5790881A
Expired / Lapsed
US
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Computer system including coprocessor devices simulating memory interfaces
Assignee: V Silicon Semiconductor Hangzhou Co Ltd
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Filing: 1995-02-07
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Granted: 1998-08-04
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Expires: 2015-02-07
Abstract
Abstract A method and system for coupling a coprocessor to a master device, in which the coprocessor emulates an memory interface to the master device, like that of a memory device. The coprocessor is coupled to a memory bus and receives memory accesses directed to a set of addresses not covered by memory devices also coupled to the memory bus. The coprocessor is disposed to receive data written from the master device, perform a coprocessing function on that data, and respond to a read data command from the master device with processing results. The coprocessor uses memory block transfers to read data from and write data to memory devices also coupled to the memory bus. A general purpose computer system comprises a central processor and memory coupled to a PCI bus, a graphics processor and graphics memory coupled to the PCI bus, and a coprocessor coupled to the graphics processor and graphics memory. The coprocessor is adapted to compute, in response to data written to it by the graphics processor, a graphical function such as a 3D processing function, MPEG video compression or decompression, a raytracing function, or some related function in support of graphics processing. The coprocessor may communicate with the central processor and its memory using a memory access operation performed by the central processor, and may communicate with the graphics memory using a memory block transfer performed by the graphics processor. The coprocessor may emulate a memory wait condition or memory wait state using read-ready and write-ready flags which are readable by software executing on the general processor.
Inventors
- 👤 Julien T. Nguyen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:05
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3877; G06F9/3879
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
239 words
A computer system comprising: a system bus; a first processor coupled to said system bus; a first memory bus coupled to said first processor; a memory coupled to said first memory bus; a graphics processor coupled to said system bus; a graphics memory bus coupled to said graphics processor; a graphics memory coupled to said graphics memory bus, said graphics memory being disposed to respond to a first set of addresses on said graphics memory bus; and a coprocessor coupled to said graphics memory bus, said coprocessor being disposed to respond to a second set of addresses on said graphics memory bus so as to emulate a memory device; wherein said coprocessor is disposed to receive a set of input data from said graphics memory bus when said graphics processor writes said input data to said graphics memory bus for one of said second set of memory addresses, said coprocessor is disposed to process said set of input data upon receipt to produce a set of output results, and said coprocessor is disposed to transmit said set of output results to said graphics memory bus when said graphics processor reads said output results from said graphics memory bus for one of said second set of memory addresses; and a second coprocessor coupled to said graphics memory bus and disposed to respond to a third set of addresses on said graphics memory bus so as to emulate a memory device.
Claim 2
Dependent Claim
239 words
A computer system comprising: a system bus; a first processor coupled to said system bus; a first memory bus coupled to said first processor; a memory coupled to said first memory bus; a graphics processor coupled to said system bus; a graphics memory bus coupled to said graphics processor; a graphics memory coupled to said graphics memory bus, said graphics memory being disposed to respond to a first set of addresses on said graphics memory bus; and a coprocessor coupled to said graphics memory bus, said coprocessor being disposed to respond to a second set of addresses on said graphics memory bus so as to emulate a memory device; wherein said coprocessor is disposed to receive a set of input data from said graphics memory bus when said graphics processor writes said input data to said graphics memory bus for one of said second set of memory addresses, said coprocessor is disposed to process said set of input data upon receipt to produce a set of output results, and said coprocessor is disposed to transmit said set of output results to said graphics memory bus when said graphics processor reads said output results from said graphics memory bus for one of said second set of memory addresses; and a second coprocessor coupled to said graphics memory bus and disposed to respond to a third set of addresses on said graphics memory bus so as to emulate a memory device.
Claim 3
Dependent Claim
47 words
The system in claim 1, comprising a display; wherein said coprocessor is disposed to compute, in response to said input data, a graphical function responsive to said input data; and said graphics processor is disposed to present an image on said display responsive to said graphical function.
Claim 4
Dependent Claim
34 words
The system in claim 2, wherein said graphical function comprises a 3D graphics function, a graphics compression function, a graphics decompression function, a JPEG image function, an MPEG video function, or a raytracing function.
Claim 5
Dependent Claim
27 words
The system in claim 1, wherein said graphics processor is adapted to perform a memory operation communicating a data item between said graphics memory and said coprocessor.
Claim 6
Independent Claim
210 words
A method for coupling computer system devices, said method comprising the steps of: coupling a system bus to a processor; directly coupling said processor and a memory to a memory bus, said memory bus comprising a set of control signal lines, a set of address lines, and a set of data lines; directly coupling a coprocessor to said memory bus; reserving a first set of memory addresses for said memory, and reserving a second set of memory addresses for said coprocessor; disposing said coprocessor to emulate a memory device so as to receive a set of input data from said memory bus when said processor writes said input data to said memory bus for one of said second set of memory addresses; disposing said coprocessor to emulate a memory device so as to process said set of input data upon receipt to produce a set of output results; and disposing said coprocessor to emulate a memory device so as to transmit said set of output results to said memory bus when said processor reads said output results from said memory bus for one of said second set of memory addresses; coupling a second coprocessor to said memory bus; and reserving a third set of memory addresses for said second coprocessor.
Claim 7
Independent Claim
210 words
A method for coupling computer system devices, said method comprising the steps of: coupling a system bus to a processor; directly coupling said processor and a memory to a memory bus, said memory bus comprising a set of control signal lines, a set of address lines, and a set of data lines; directly coupling a coprocessor to said memory bus; reserving a first set of memory addresses for said memory, and reserving a second set of memory addresses for said coprocessor; disposing said coprocessor to emulate a memory device so as to receive a set of input data from said memory bus when said processor writes said input data to said memory bus for one of said second set of memory addresses; disposing said coprocessor to emulate a memory device so as to process said set of input data upon receipt to produce a set of output results; and disposing said coprocessor to emulate a memory device so as to transmit said set of output results to said memory bus when said processor reads said output results from said memory bus for one of said second set of memory addresses; coupling a second coprocessor to said memory bus; and reserving a third set of memory addresses for said second coprocessor.
Claim 8
Dependent Claim
39 words
The method in claim 5, further comprising a step of providing a read-ready flag at said coprocessor, said read-ready flag having a fist read-ready state representative of a condition wherein said coprocessor is ready to transmit said output results.
Claim 9
Dependent Claim
36 words
The method in claim 6, further comprising a step of disposing said processor to test said read-ready flag before performing a read operation on said memory bus for one of said second set of memory addresses.
Claim 10
Dependent Claim
39 words
The method in claim 5, further comprising a step of providing a write-ready flag at said coprocessor, said write-ready flag having a fist write-ready state representative of a condition wherein said coprocessor is ready to receive said input data.
Claim 11
Dependent Claim
36 words
The method in claim 8, further comprising a step of disposing said processor to test said write-ready flag before performing a write operation on said memory bus for one of said second set of memory addresses.
Claim 12
Dependent Claim
42 words
The method in claim 5, further comprising a step of disposing said coprocessor to receive a second set of data from said memory when said processor triggers a memory block transfer between a memory coupled to said memory bus and said coprocessor.
Claim 13
Dependent Claim
42 words
The method in claim 5, further comprising a step of disposing said coprocessor to transmit a second set of data to said memory when said processor triggers a memory block transfer between a memory coupled to said memory bus and said coprocessor.
Claim 14
Dependent Claim
38 words
The method in claim 5, wherein said processor is a graphics processor, said input data are graphics data, and said output results are graphics data, and comprising presenting an image on a display responsive to said output results.
Claim 15
Dependent Claim
207 words
A circuit comprising: a memory bus having a set of control signal lines disposed to communicate a write enable control signal, a set of address lines, and a set of data lines; a processor coupled directly to said memory bus, said processor having a memory address register coupled to said set of address lines and a memory data register coupled to said set of data lines; a memory coupled to said memory bus, said memory being disposed to respond to a first set of memory addresses appearing on said set of address lines; a coprocessor directly coupled to said memory bus, said coprocessor being disposed emulate a memory device so as to respond to a second set of memory addresses appearing on said set of address lines, and having means for performing a computation responsive to said set of data lines and a first state of said write enable control signal, and means for reporting a result of said computation responsive to said set of address lines and a second state of said write enable control signal; and a second coprocessor coupled to said memory bus and disposed to respond to a third set of addresses appearing on said set of address lines on said memory bus.
Claim 16
Dependent Claim
207 words
A circuit comprising: a memory bus having a set of control signal lines disposed to communicate a write enable control signal, a set of address lines, and a set of data lines; a processor coupled directly to said memory bus, said processor having a memory address register coupled to said set of address lines and a memory data register coupled to said set of data lines; a memory coupled to said memory bus, said memory being disposed to respond to a first set of memory addresses appearing on said set of address lines; a coprocessor directly coupled to said memory bus, said coprocessor being disposed emulate a memory device so as to respond to a second set of memory addresses appearing on said set of address lines, and having means for performing a computation responsive to said set of data lines and a first state of said write enable control signal, and means for reporting a result of said computation responsive to said set of address lines and a second state of said write enable control signal; and a second coprocessor coupled to said memory bus and disposed to respond to a third set of addresses appearing on said set of address lines on said memory bus.
Claim 17
Dependent Claim
37 words
The circuit in claim 13, further comprising a step of a read-ready flag at said coprocessor, said read-ready flag having a first read-ready state representative of a condition wherein said coprocessor is ready to transmit said result.
Claim 18
Dependent Claim
33 words
The circuit in claim 13, further comprising means for testing said read-ready flag before said processor performs a read operation on said memory bus for one of said second set of memory addresses.
Claim 19
Dependent Claim
34 words
The circuit in claim 13, further comprising a write-ready flag at said coprocessor, said write-ready flag having a first write-ready state representative of a condition wherein said coprocessor is ready to perform said computation.
Claim 20
Dependent Claim
33 words
A circuit as in claim 16, comprising means for testing said write-ready flag before said processor performs a write operation on said memory bus for one of said second set of memory addresses.
Claim 21
Dependent Claim
42 words
The circuit as in claim 13, wherein said control signal lines are disposed to communicate a block transfer control signal, and said memory is disposed to communicate a set of data items with said coprocessor responsive to said block transfer control signal.
References Cited (Backward Citations)
US3846762A
Cited
US3947826A
Cited
US4353057A
Cited
US4528561A
Cited
US4394650A
Cited
US4425581A
Cited
US4587633A
Cited
US4757310A
Cited
US4684936A
Cited
US4779210A
Cited
US4811205A
Cited
US4628479A
Cited
US4947342A
Cited
US5333261A
Cited
US4905189A
Cited
US4905189B1
Cited
US4862392A
Cited
US5065346A
Cited
US4876600A
Cited
US4870406A
Cited
US4916301A
Cited
US5191410A
Cited
US5046023A
Cited
US4953101A
Cited
US5329630A
Cited
US5157716A
Cited
US5208745A
Cited
US4947257A
Cited
EP0384257A2
Cited
US4994912A
Cited
EP0384419A2
Cited
US5231492A
Cited
US5138307A
Cited
US5111409A
Cited
US5220312A
Cited
US5397853A
Cited
US5097257A
Cited
US5253078A
Cited
US5196946A
Cited
US5191548A
Cited
US5270832A
Cited
US5341318A
Cited
US5151875A
Cited
US5168356A
Cited
US5122875A
Cited
US5111292A
Cited
US5379356A
Cited
US5309567A
Cited
US5450544A
Cited
US5289276A
Cited
US5426756A
Cited
US5371861A
Cited
US5446501A
Cited
US5402147A
Cited
US5471576A
Cited
US5406306A
Cited
US5392239A
Cited
US5526503A
Cited
US5434913A
Cited
US5450542A
Cited
US5416749A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-03 | 2002-02-02 | 2002-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-03 | 2006-02-02 | 2006-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-03 | 2010-02-02 | 2010-08-04 | $7700.00 | Window Closed / Lapsed |