Geometry processor for graphics display system

Claim 2

A programmable electronic geometry processor circuit for use in a graphics display system that includes a database memory for storing segments of graphics data which represent three-dimensional objects to be displayed and which contain operation codes pertaining to the objects, a first processing means for writing segments of graphics data into the memory, a second processing means responsive to the first processing means for sequentially fetching graphics data stored in the memory and placing such fetched graphics data on a dedicated memory bus, and a third processing means for accepting processed graphics data from the geometry processor for display on a display device, where the geometry processor includes: a. an input register means coupled to the memory by the dedicated memory bus, for temporarily storing graphics data fetched from the memory by the second processing means; b. a buffer register means coupled to the second processing means by a dedicated stack bus, for buffering data transferred between the second processing means and the geometry processor; c. an arithmetic pipeline module, coupled to the input and buffer register means, for mathematically processing graphics data temporarily stored in the input register means or the buffer register means; d. an output register means coupled to the arithmetic pipeline module and to the buffer register means, for temporarily storing the output of the arithmetic pipeline module; and e. a microcontroller means, coupled to the first and third processing means by a system bus, to the input, buffer, and output register means, and to the arithmetic pipeline module, for accepting from the first processing means a sequence of processing instructions, storing the instructions in an instruction memory, and selectively executing the instructions in response to the operation codes stored in each segment of graphics data, to: (1) select during a first processing phase from the input register means and temporarily transfer to the second processing means over the stack bus only segments containing data that is at least partly within a defined viewing volume, (2) accept during a second processing phase the selected segments from the second processing means over the stack bus and associated graphics data from the memory fetched by the second processing means over the dedicated memory bus, and use the arithmetic pipeline module to transform the graphics data from a three-dimensional representation to a two-dimensional representation, and (3) transfer the transformed graphics data to the third processing means over the system bus for display.

Claim 3

The geometry processor of claim 1, wherein the register means are double-buffered.

Claim 4

The geometry processor of claim 1, further including intermediate register means, coupled to the input of the arithmetic pipeline module and the output register means, for temporarily storing intermediate calculation values during processing of graphics data and selectively transferring intermediate calculation values to the arithmetic pipeline module for further processing.

Claim 5

The geometry processor of claim 2, wherein the arithmetic pipeline module comprises a dynamically reconfigurable calculation pipeline, including: a. a multiplier circuit, coupled to the inputs of the arithmetic pipeline module, for multiplying two input numbers; b. an accumulator circuit, coupled to the multiplier circuit, for adding a sequence of products from the multiplier circuit; c. a multifunction arithmetic logic unit, coupled to the inputs of the arithmetic pipeline module and to the output of the accumulator circuit, for selectively operating on input data or upon the output sum of the accumulator circuit; d. a linear approximation transform circuit, coupled to the output of the accumulator circuit, for selectively operating on the output sum of the accumulator circuit; and e. a bus buffer circuit, coupled to the output of the accumulator circuit, for selectively coupling the output sum of the accumulator circuit to the output register means.

Claim 6

The geometry processor of claim 1, further including a delay logic circuit coupled to the microcontroller means and the arithmetic pipeline module for selectively delaying the transmittal of portions of instructions to the arithmetic pipeline module to coincide with the processing of data therein.

Claim 7

A programmable electronic geometry processor circuit adapted for use in a graphics display system that includes a database memory for storing segments of graphics data which represent three-dimensional objects to be displayed and which contain operation codes pertaining to the objects, a first processing means for writing segments of graphics data into the memory, a second processing means responsive to the first processing means for sequentially fetching graphics data stored in the memory and placing such fetched graphics data on a dedicated memory bus, and a third processing means for accepting processed graphics data from the geometry processor for display on a display device, where the geometry processor includes: a. a double buffered input register means coupled to the memory by the dedicated memory bus, for temporarily storing graphics data fetched from the memory by the second processing means; b. a double buffered buffer register means coupled to the second processing means by a dedicated stack bus, for buffering data transferred between the second processing means and the geometry processor; c. an arithmetic pipeline module, coupled to the input and buffer register means, for mathematically processing graphics data temporarily stored in the input register means or the buffer register means; d. a double buffered output register means coupled to the arithmetic pipeline module and to the buffer register means, for temporarily storing the output of the arithmetic pipeline module; e. an intermediate register means, coupled to the arithmetic pipeline module and the output register means, for temporarily storing intermediate calculation values during processing of graphics data; f. a microcontroller means, coupled to the first and third processing means by a system bus, to the input, buffer, and output register means, and to the arithmetic pipeline module, for accepting from the first processing means a sequence of processing instructions, storing the instructions in an instruction memory, and selectively executing the instructions in response to the operation codes stored in each segment of graphics data, to: (1) select during a first processing phase from the input register means and temporarily transfer to the second processing means over the stack bus only segments containing data that is at least partly within a defined viewing volume, (2) accept during a second processing phase the selected segments from the second processing means over the stack bus and associated graphics data from the memory fetched by the second processing means over the dedicated memory bus, and use the arithmetic pipeline module to transform the graphics data from a three-dimensional representation to a two-dimensional representation, and (3) transfer the transformed graphics data to the third processing means over the system bus for display.

Claim 8

A programmable electronic geometry processor circuit adapted for use in a graphics display system that includes a database memory for storing segments of graphics data which represent three-dimensional objects to be displayed and which contain operation codes pertaining to the objects, a first processing means for writing segments of graphics data into the memory, a second processing means responsive to the first processing means for sequentially fetching graphics data stored in the memory and placing such fetched graphics data on a dedicated memory bus, and a third processing means for accepting processed graphics data from the geometry processor for display on a display device, where the geometry processor includes: a. a double buffered input register means coupled to the memory by the dedicated memory bus, for temporarily storing graphics data fetched from the memory by the second processing means; b. a double buffered buffer register means coupled to the second processing means by a dedicated stack bus, for buffering data transferred between the second processing means and the geometry processor; c. an arithmetic pipeline module, coupled to the input and buffer register means, for mathematically processing graphics data temporarily stored in the input register means or the buffer register means; d. a double buffered output register means coupled to the arithmetic pipeline module and to the buffer register means, for temporarily storing the output of the arithmetic pipeline module; e. an intermediate register means, coupled to the arithmetic pipeline module and the output register means, for temporarily storing intermediate calculation values during processing of graphics data; f. a microcontroller means, coupled to the first and third processing means by a system bus, to the input, buffer, and output register means, and to the arithmetic pipeline module, for accepting from the first processing means a sequence of processing instructions, storing the instructions in an instruction memory, and selectively executing the instructions in response to the operation codes stored in each segment of graphics data, to: (1) select during a first processing phase from the input register means and temporarily transfer to the second processing means over the stack bus only segments containing data that is at least partly within a defined viewing volume, (2) accept during a second processing phase the selected segments from the second processing means over the stack bus and associated graphics data from the memory fetched by the second processing means over the dedicated memory bus, and use the arithmetic pipeline module to transform the graphics data from a three-dimensional representation to a two-dimensional representation, and (3) transfer the transformed graphics data to the third processing means over the system bus for display.

Claim 9

The geometry processor of claim 6, wherein the arithmetic pipeline module comprises a dynamically reconfigurable calculation pipeline, including: a. a multiplier circuit, coupled to the inputs of the arithmetic pipeline module, for multiplying two input numbers; b. an accumulator circuit, coupled to the multiplier circuit, for adding a sequence of products from the multiplier circuit; c. a multifunction arithmetic logic unit, coupled to the inputs of the arithmetic pipeline module and to the output of the accumulator circuit, for selectively operating on input data or upon the output sum of the accumulator circuit; d. a linear approximation transform circuit, coupled to the output of the accumulator circuit, for selectively operating on the output sum of the accumulator circuit; and e. a bus buffer circuit, coupled to the output of the accumulator circuit, for selectively coupling the output sum of the accumulator circuit to the output register means.

Claim 10

The geometry processor of claim 6, further including a delay logic circuit coupled to the microcontroller means and the arithmetic pipeline module for selectively delaying the transmittal of portions of instructions to the arithmetic pipeline module to coincide with the processing of data therein.