US5526503A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Virtual addressing buffer circuit
Assignee: Samsung Electronics Co Ltd
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Filing: 1993-10-06
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Granted: 1996-06-11
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Expires: 2013-10-06
Abstract
Abstract A virtual addressing buffer circuit has improved address mapping and control flexibility for improved physical resource management and a unique opportunity for forward-compatible system design. The virtual addressing buffer formats the output address utilizing a format register as a combination of the new address bits and the original input address bits. The ability to format the output address enables the user to replace certain address bits without requiring that the entire address be replaced. The virtual addressing buffer controls the output of several command signals to external circuits to indicate how the system should respond to the address output from the virtual addressing buffer. The command signals are controlled by a command register and are output from the virtual addressing buffer only when an address match has been verified. The virtual addressing buffer circuit filters out certain bits of an input address as indicated by a filter register before it verifies that the input address matches a stored address. The bit pattern in the filtering register is not fixed, so any bit location in the input address can be filtered out before the address is verified. Once an address match has been detected, the virtual addressing buffer circuit replaces the entire input address with a new formatted address.
Inventors
- 👤 Jason S. Kim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 22:49
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F11/00; G06F11/22; G06F11/26; G06F11/261; G06F12/1027; G06F13/00; G06F13/10; G06F13/105
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
102 words
A virtual addressing buffer circuit wherein an input address is translated into an output address, said virtual addressing buffer circuit comprises: a filtering and verification portion for comparing a stored match address to an input address and for filtering out any bits of the input address which are not relevant to a determination of whether the input address matches the stored match address; a formatting portion for generating a formatted output address from a translated address and from said input address; and a translation portion for selecting between said input address and said formatted output address for output as said output address.
Claim 2
Dependent Claim
102 words
A virtual addressing buffer circuit wherein an input address is translated into an output address, said virtual addressing buffer circuit comprises: a filtering and verification portion for comparing a stored match address to an input address and for filtering out any bits of the input address which are not relevant to a determination of whether the input address matches the stored match address; a formatting portion for generating a formatted output address from a translated address and from said input address; and a translation portion for selecting between said input address and said formatted output address for output as said output address.
Claim 3
Dependent Claim
42 words
A virtual addressing buffer circuit as defined in claim 1, wherein a format address determines which address bits in said formatted output address are from said input address and which address bits in said formatted output address are from said translated address.
Claim 4
Dependent Claim
81 words
A virtual addressing buffer circuit as defined in claim 2, wherein said formatting portion comprises a plurality of 2×1 multiplexers, wherein each bit of said input address is connected to a first input of one of said 2×1 multiplexers and a corresponding bit of said translate address is connected to a second input of said one of said 2×1 multiplexers and a corresponding bit of said format address is connected to a select input of said one of said 2×1 multiplexers.
Claim 5
Dependent Claim
41 words
A virtual addressing buffer circuit as defined in claim 1, wherein said filtering and verification portion outputs a HIT signal which indicates when the relevant bits of said input address are equivalent to the corresponding bits of said stored match address.
Claim 6
Dependent Claim
75 words
A virtual addressing buffer circuit as defined in claim 4, wherein said translation portion comprises a multiple-bit 2×1 multiplexer, a first input of said multiple-bit 2×1 multiplexer is connected to said input address, a second input of said multiple-bit 2×1 multiplexer is connected to said formatted output address and said select input is connected to said HIT signal for selecting between said input address and said formatted output address for output as said output address.
Claim 7
Independent Claim
100 words
A method of translating an input address to a translated output address comprising the steps of: comparing a stored match address to said input address; filtering out any bits of said address comparison which are not relevant to a determination of whether the input address is to be translated; generating a formatted output address from the bits of a translated address and said input address; and selecting between said input address and said formatted output address for output as said translated output address depending on the result of the address comparison between said stored match address and said input address.
Claim 8
Independent Claim
100 words
A method of translating an input address to a translated output address comprising the steps of: comparing a stored match address to said input address; filtering out any bits of said address comparison which are not relevant to a determination of whether the input address is to be translated; generating a formatted output address from the bits of a translated address and said input address; and selecting between said input address and said formatted output address for output as said translated output address depending on the result of the address comparison between said stored match address and said input address.
Claim 9
Dependent Claim
84 words
The method of translating an input address as described in claim 6 additionally comprising the steps of: providing a set of command signals, each of said command signals having a respective preset condition, each preset condition having an active level and an inactive level; and outputting a command signal at an active level if the respective preset condition of the command signal is at an active level when the relevant bits of said input address match the corresponding bits of the stored match address.
Claim 10
Independent Claim
182 words
A method of utilizing a physical memory of a computer system which is larger than the logical memory space of a CPU by enabling the use of memory blocks which are above the logical memory space of a CPU, comprising the steps of: configuring the system memory map to include a memory space above the logic memory space of the CPU; filtering out any bits of a CPU requested address which are not relevant to a determination of whether the CPU requested address matches a stored match address to provide a resultant filtered CPU requested address; comparing the resultant filtered CPU requested address to the stored match address to determine whether the CPU requested address is located above the logical memory space of the CPU; formatting an output address from a translated address and from said CPU requested address to provide a formatted output address; and selecting between said CPU requested address and said formatted output address for output as said output address based upon the results of the comparison of said resultant filtered CPU requested address to a stored match address.
Claim 11
Independent Claim
182 words
A method of utilizing a physical memory of a computer system which is larger than the logical memory space of a CPU by enabling the use of memory blocks which are above the logical memory space of a CPU, comprising the steps of: configuring the system memory map to include a memory space above the logic memory space of the CPU; filtering out any bits of a CPU requested address which are not relevant to a determination of whether the CPU requested address matches a stored match address to provide a resultant filtered CPU requested address; comparing the resultant filtered CPU requested address to the stored match address to determine whether the CPU requested address is located above the logical memory space of the CPU; formatting an output address from a translated address and from said CPU requested address to provide a formatted output address; and selecting between said CPU requested address and said formatted output address for output as said output address based upon the results of the comparison of said resultant filtered CPU requested address to a stored match address.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-11 | 1999-12-11 | 2000-06-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-11 | 2003-12-11 | 2004-06-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-11 | 2007-12-11 | 2008-06-11 | $7700.00 | Window Closed / Lapsed |