Memory controller for using reserved DRAM addresses for EMS

Claim 2

A memory control circuit for controlling access to a memory, comprising: first memory decodes means, coupled to an address bus, for providing a first memory timing enable signal when an address on said address bus is within a first predetermined range of addresses and is not within a reserved group of addresses within said first range of addresses; second expanded memory space (EMS) decode means, coupled to said address bus, for providing a translated address which is within said reserved group of addresses and a second EMS timing enable signal when an address on said address bus is within a predetermined window of addresses; and memory control signal generation means, responsive to either said first memory timing enable signal or said second EMS timing enable signal, for providing memory control signals to access said memory.

Claim 3

The memory control circuit of claim 1 wherein said memory is DRAM memory and said memory control signal generation means is a DRAM timing circuit which provides row address strobe (RAS) and column address strobe (CAS) signals to said DRAM.

Claim 4

The memory control circuit of claim 2 wherein said reserved group of addresses includes addresses used for video RAM and BIOS ROM.

Claim 5

The memory control circuit of claim 2 further comprising at least one configuration register for storing a first address to determine said first predetermined range of addresses and a second address which is less than the amount of installed DRAM for restricting direct processing access to said first predetermined range.

Claim 6

A memory control circuit for controlling access to a memory, comprising: DRAM decode means, coupled to an address bus, for providing a DRAM enable a signal when an address on said address bus is within a first predetermined range of addresses and is not within a reserved group of addresses within said first range of addresses: expanded memory spaced (EMS) decode means, coupled to said address bus, for providing a translated address which is within said reserved group of addresses and an EMS enable signal when said address on said address bus is within a predetermined window of addresses; and means for providing said translated address to said memory when said EMS enable signal is active and providing said address to said memory when said EMS enable signal is not active and said DRAM enable signal is active.

Claim 7

A memory control circuit for controlling access to a memory, comprising: DRAM decode means, coupled to an address bus, for providing a DRAM enable a signal when an address on said address bus is within a first predetermined range of addresses and is not within a reserved group of addresses within said first range of addresses: expanded memory spaced (EMS) decode means, coupled to said address bus, for providing a translated address which is within said reserved group of addresses and an EMS enable signal when said address on said address bus is within a predetermined window of addresses; and means for providing said translated address to said memory when said EMS enable signal is active and providing said address to said memory when said EMS enable signal is not active and said DRAM enable signal is active.

Claim 8

The circuit of claim 5 wherein said means for providing includes a first multiplexer for selecting between high order bits of said address and high order bits of said translated address responsive to said EMS enable signal.

Claim 9

The circuit of claim 6 further comprising a RAS generator coupled to at least a portion of an output of said first multiplexer.

Claim 10

The circuit of claim 6 further comprising a second multiplexer having a first input coupled to an output of said first multiplexer and a second input coupled to an output of said DRAM decode means.

Claim 11

A memory control circuit for controlling access to a memory, comprising: DRAM decode means, coupled to an address bus, for providing a DRAM enable signal when an address on said address bus is within a first predetermined range of addresses and is not within a reserved group of addresses within said first range of addresses; expanded memory space (EMS) decode means, coupled to said address bus, for providing a translated address within said reserved group of addresses and an EMS enable signal when said address on said address bus is within a predetermined window of addresses; means for providing said translated address to said memory when said EMS enable signal is active and providing said address to said memory when said EMS enable signal is not active and said DRAM enable signal is active, said means for providing including a first multiplexer for selecting between high order bits of said address and high order bits of said translated address responsive to said EMS enable signal; and a RAS generator coupled to at least a portion of an output of said first multiplexer.

Claim 12

A memory control circuit for controlling access to a memory, comprising: DRAM decode means, coupled to an address bus, for providing a DRAM enable signal when an address on said address bus is within a first predetermined range of addresses and is not within a reserved group of addresses within said first range of addresses; expanded memory space (EMS) decode means, coupled to said address bus, for providing a translated address within said reserved group of addresses and an EMS enable signal when said address on said address bus is within a predetermined window of addresses; means for providing said translated address to said memory when said EMS enable signal is active and providing said address to said memory when said EMS enable signal is not active and said DRAM enable signal is active, said means for providing including a first multiplexer for selecting between high order bits of said address and high order bits of said translated address responsive to said EMS enable signal; and a RAS generator coupled to at least a portion of an output of said first multiplexer.