US4985871A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory controller for using reserved dram addresses for expanded memory space
Assignee: Intel Corp
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Filing: 1989-11-13
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Granted: 1991-01-15
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Expires: 2009-11-13
Abstract
Abstract A memory controller which can map expanded memory space (EMS) addresses into the dynamic random access memory (DRAM) behind video random access memory (RAM) addresses or other reserved areas of memory. A single chip has both a DRAM decoder and an EMS decoder operating in parallel. A DRAM decoder examines received addresses and provides an enable signal to a DRAM timing circuit if the address is within the DRAM range and not for a reserved group of addresses. A separate EMS decoder provides a translated address when a received address is within an EMS window. The EMS decoder also provides an EMS timing signal to the DRAM timing circuit.
Inventors
- 👤 Robert W. Catlin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 19:56
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/12; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/408; G11C11/4087
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
165 words
A memory control circuit for controlling access to a memory, comprising: first memory decode means, coupled to an address bus, for providing a first memory timing enable signal when an address on said address bus is within a first predetermined range of addresses and is not within a reserved group of addresses within said first range of addresses; expanded memory space (EMS) decode means, coupled to said address bus, for providing a translated address and an EMS timing enable signal when an address on said address bus is within a second predetermined range of addresses; memory control signal generation means, responsive to either said first memory timing enable signal or said EMS timing enable signal, for providing memory control signals to access said memory; whereby said EMS decode means provides translated addresses within said reserved group of addresses; and an OR gate for providing one of said first memory timing enable signal and said EMS timing enable signal to said memory control signal generation means.
Claim 2
Dependent Claim
165 words
A memory control circuit for controlling access to a memory, comprising: first memory decode means, coupled to an address bus, for providing a first memory timing enable signal when an address on said address bus is within a first predetermined range of addresses and is not within a reserved group of addresses within said first range of addresses; expanded memory space (EMS) decode means, coupled to said address bus, for providing a translated address and an EMS timing enable signal when an address on said address bus is within a second predetermined range of addresses; memory control signal generation means, responsive to either said first memory timing enable signal or said EMS timing enable signal, for providing memory control signals to access said memory; whereby said EMS decode means provides translated addresses within said reserved group of addresses; and an OR gate for providing one of said first memory timing enable signal and said EMS timing enable signal to said memory control signal generation means.
Claim 3
Dependent Claim
156 words
A memory control circuit for controlling access to a memory, comprising: first memory decode means, coupled to an address bus, for providing a first memory timing enable signal when an address on said address bus within a first predetermined range of addresses and is not within a reserved group of addresses within said first range of addresses; expanded memory space (EMS) decode means, coupled to said address bus, for providing a translated address and an EMS timing enable signal when an address on said address bus is within a second predetermined range of addresses; memory control signal generation means, responsive to either said first memory timing enable signal or said EMS timing enable signal, for providing memory control signals to access said memory; whereby said EMS decode means provides translated addresses within said reserved group of addresses; and wherein said EMS timing enable signal is generated from a page enable bit in an EMS translation register.
Claim 4
Dependent Claim
156 words
A memory control circuit for controlling access to a memory, comprising: first memory decode means, coupled to an address bus, for providing a first memory timing enable signal when an address on said address bus within a first predetermined range of addresses and is not within a reserved group of addresses within said first range of addresses; expanded memory space (EMS) decode means, coupled to said address bus, for providing a translated address and an EMS timing enable signal when an address on said address bus is within a second predetermined range of addresses; memory control signal generation means, responsive to either said first memory timing enable signal or said EMS timing enable signal, for providing memory control signals to access said memory; whereby said EMS decode means provides translated addresses within said reserved group of addresses; and wherein said EMS timing enable signal is generated from a page enable bit in an EMS translation register.
Claim 5
Dependent Claim
176 words
A memory control circuit for controlling access to a memory, comprising: first memory decode means, coupled to an address bus, for providing a first memory timing enable signal when an address on said address bus is within a first predetermined range of addresses and is not within a reserved group of addresses within said first range of addresses; expanded memory space (EMS) decode means, coupled to said address bus, for providing a translated address and an EMS timing enable signal when an address on said address bus is within a second predetermined range of addresses; memory control signal generation means, responsive to either said first memory timing enable signal or said EMS timing enable signal, for providing memory control signals to access said memory; whereby said EMS decode means provides translated addresses within said reserved group of addresses; and a first multiplexer having a first input coupled to receive said translated addresses, a second input coupled to receive a corresponding portion of said address, and a select input coupled to receive said EMS timing enable signal.
Claim 6
Dependent Claim
176 words
A memory control circuit for controlling access to a memory, comprising: first memory decode means, coupled to an address bus, for providing a first memory timing enable signal when an address on said address bus is within a first predetermined range of addresses and is not within a reserved group of addresses within said first range of addresses; expanded memory space (EMS) decode means, coupled to said address bus, for providing a translated address and an EMS timing enable signal when an address on said address bus is within a second predetermined range of addresses; memory control signal generation means, responsive to either said first memory timing enable signal or said EMS timing enable signal, for providing memory control signals to access said memory; whereby said EMS decode means provides translated addresses within said reserved group of addresses; and a first multiplexer having a first input coupled to receive said translated addresses, a second input coupled to receive a corresponding portion of said address, and a select input coupled to receive said EMS timing enable signal.
Claim 7
Dependent Claim
46 words
The memory control circuit of claim 3 further comprising a second multiplexer having a first input coupled to an output of said first multiplexer, a second input coupled to receive lower order address bits of said address and a third input coupled to receive refresh addresses.
Claim 8
Dependent Claim
26 words
The memory control circuit of claim 3 further comprising row address strobe (RAS) generation logic having an input coupled to an output of said first multiplexer.
Claim 9
Dependent Claim
259 words
A memory control circuit for controlling access to a DRAM memory, comprising: first DRAM memory decode means, coupled to an address bus, for providing a first DRAM timing enable signal when an address on said address bus is within a first predetermined range of addresses and is not within a reserved group of addresses within said first range of addresses; expanded memory space (EMS) decode means, coupled to said address bus, for providing a translated address and an EMS timing enable signal when an address on said address bus is within a second predetermined range of addresses; DRAM control signal generation means, responsive to either said first DRAM timing enable signal or said EMS timing enable signal, for providing memory control signals to access said DRAM memory; whereby said EMS decode means provides translated addresses within said reserved group of addresses; an OR gate for providing one of said first DRAM timing enable signal and said EMS timing enable signal to said DRAM control signal generation means; a first multiplexer having a first input coupled to receive said translated addresses, a second input coupled to receive a corresponding portion of said address, and a select input coupled to receive said EMS timing enable signal; a second multiplexer having a first input coupled to an output of said first multiplexer, a second input coupled to receive lower order address bits of said address and a third input coupled to receive refresh addresses; and row address strobe (RAS) generation logic having an input coupled to an output of said first multiplexer.
Claim 10
Dependent Claim
259 words
A memory control circuit for controlling access to a DRAM memory, comprising: first DRAM memory decode means, coupled to an address bus, for providing a first DRAM timing enable signal when an address on said address bus is within a first predetermined range of addresses and is not within a reserved group of addresses within said first range of addresses; expanded memory space (EMS) decode means, coupled to said address bus, for providing a translated address and an EMS timing enable signal when an address on said address bus is within a second predetermined range of addresses; DRAM control signal generation means, responsive to either said first DRAM timing enable signal or said EMS timing enable signal, for providing memory control signals to access said DRAM memory; whereby said EMS decode means provides translated addresses within said reserved group of addresses; an OR gate for providing one of said first DRAM timing enable signal and said EMS timing enable signal to said DRAM control signal generation means; a first multiplexer having a first input coupled to receive said translated addresses, a second input coupled to receive a corresponding portion of said address, and a select input coupled to receive said EMS timing enable signal; a second multiplexer having a first input coupled to an output of said first multiplexer, a second input coupled to receive lower order address bits of said address and a third input coupled to receive refresh addresses; and row address strobe (RAS) generation logic having an input coupled to an output of said first multiplexer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-14 | 1994-07-16 | 1995-01-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-14 | 1998-07-16 | 1999-01-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-14 | 2002-07-16 | 2003-01-15 | $7700.00 | Window Closed / Lapsed |