Pipeline display control apparatus with logic for blocking graphics processor accesses to shared memory during selected main processor graphics operations

Claim 1

A graphics display apparatus comprising a terminal control unit having input/output devices connected thereto and including a data processor connected to control the terminal control unit and to receive high-level graphic image orders defining a graphical image from a host processor, a display monitor connected to said terminal control unit by means of display control logic incorporating a graphics processor connected to receive low-level graphic orders from said data processor via a shared memory and to control loading of bit patterns representing said graphical image into a display refresh buffer, and means for reading the contents of said refresh buffer to display said graphical image on said display monitor, wherein said low-level graphic orders are stored in said shared memory which is connected to said data processor and said graphic processor, said data processor, shared memory and graphics processor comprise a pipeline which is controlled by pipeline control logic means for blocking said graphics processor from accessing said shared memory until after said data processor has completed processing of each high-level graphic order into a complete sequence of low-level graphic orders and storing said complete sequence of low-level graphic orders into said shared memory, and to allow said graphics processor to access said shared memory and to process said sequence of low-level orders after completion of processing of the associated high level order by the data processor.