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US5790836A
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Apparatus for simulating digital signal processing circuits
Assignee: Panasonic Holdings Corp
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Filing: 1996-08-23
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Granted: 1998-08-04
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Expires: 2016-08-23
Abstract
Abstract Test vector storing means outputs data for simulation at a predetermined transfer speed. A signal processor executes the simulation of a digital signal processing circuit by using the data for simulation and outputs the simulation result. Simulation result storing means stores the simulation result input at a predetermined transfer speed. Simulation program generating means generates a simulation program, in advance, which is executed by the signal processor and has throughput that is coincident with the output speed of data of the test vector storing means. Synchronizing means synchronizes the data transfer of the test vector storing means, the execution speed of the signal processor, and the data transfer of the simulation result storing means.
Inventors
- 👤 Masanobu Mizuno
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 16:25
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/263; G06F11/2635; G06F11/2268; G06F11/261; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
198 words
An apparatus for simulating a digital signal processing circuit comprising verifying means for verifying the result of design at a register transfer level in the digital signal processing circuit by using a signal processor, the verifying means including: test vector storing means for storing data for simulation to output the data for simulation at a predetermined transfer speed; a signal processor for inputting the data for simulation output from the test vector storing means, executing the simulation of the digital signal processing circuit and outputting the simulation result; simulation result storing means for inputting the simulation result output from the signal processor at a predetermined transfer speed to store the input simulation result; simulation program generating means for generating a simulation program which is executed by the signal processor and has throughput that is coincident with the output speed of the data of the test vector storing means; and synchronizing means for synchronizing a timing at which the data for simulation is transferred from the test vector storing means, a speed timing at which the simulation is executed by the signal processor, and a timing at which the simulation result is transferred to the simulation result storing means.
Claim 2
Independent Claim
198 words
An apparatus for simulating a digital signal processing circuit comprising verifying means for verifying the result of design at a register transfer level in the digital signal processing circuit by using a signal processor, the verifying means including: test vector storing means for storing data for simulation to output the data for simulation at a predetermined transfer speed; a signal processor for inputting the data for simulation output from the test vector storing means, executing the simulation of the digital signal processing circuit and outputting the simulation result; simulation result storing means for inputting the simulation result output from the signal processor at a predetermined transfer speed to store the input simulation result; simulation program generating means for generating a simulation program which is executed by the signal processor and has throughput that is coincident with the output speed of the data of the test vector storing means; and synchronizing means for synchronizing a timing at which the data for simulation is transferred from the test vector storing means, a speed timing at which the simulation is executed by the signal processor, and a timing at which the simulation result is transferred to the simulation result storing means.
Claim 3
Dependent Claim
45 words
The apparatus for simulating the digital signal processing circuit of claim 1, wherein the simulation program generating means generates a simulation program for simulating operation between registers of a data path which is obtained as a result of design of the digital signal processing circuit.
Claim 4
Dependent Claim
74 words
The apparatus for simulating the digital signal processing circuit of claim 2, wherein the data path includes a plurality of registers; the signal processor includes a plurality of signal processing units; and the simulation program generating means includes partial data path generating means for dividing the data path for each register to generate a plurality of partial data paths, and unit allocating means for allocating the partial data path to the signal processing unit.
Claim 5
Dependent Claim
47 words
The apparatus for simulating the digital signal processing circuit of claim 1, wherein the verifying means further includes register arrangement changing means for changing the arrangement of the registers of the data path which is obtained as a result of design of the digital signal processing circuit.
Claim 6
Dependent Claim
50 words
The apparatus for simulating the digital signal processing circuit of claim 1, wherein the verifying means further includes transfer speed adjusting means for adjusting the transfer speed of the data for simulation of the test vector storing means and that of the simulation result of the simulation result storing means.
Claim 7
Dependent Claim
51 words
The apparatus for simulating the digital signal processing circuit of claim 5, wherein the transfer speed adjusting means adjusts the transfer speed of the data for simulation and that of the simulation result according to the throughput of the simulation program which can be generated by the simulation program generating means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-03 | 2002-02-02 | 2002-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-03 | 2006-02-02 | 2006-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-03 | 2010-02-02 | 2010-08-04 | $7700.00 | Window Closed / Lapsed |